From 87fbafba7885c18da21508992db14b0d1e1c7f24 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Sat, 18 Oct 2025 16:51:47 -0700 Subject: [PATCH] KNOWNBUG for unsized integer literals --- .../expressions/integer_literals3.desc | 9 ++++++++ .../verilog/expressions/integer_literals3.sv | 22 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 regression/verilog/expressions/integer_literals3.desc create mode 100644 regression/verilog/expressions/integer_literals3.sv diff --git a/regression/verilog/expressions/integer_literals3.desc b/regression/verilog/expressions/integer_literals3.desc new file mode 100644 index 000000000..761c08299 --- /dev/null +++ b/regression/verilog/expressions/integer_literals3.desc @@ -0,0 +1,9 @@ +KNOWNBUG +integer_literals3.sv + +^EXIT=0$ +^SIGNAL=0$ +-- +^warning: ignoring +-- +The context-dependent extension is not implemented. diff --git a/regression/verilog/expressions/integer_literals3.sv b/regression/verilog/expressions/integer_literals3.sv new file mode 100644 index 000000000..ed4d70bd4 --- /dev/null +++ b/regression/verilog/expressions/integer_literals3.sv @@ -0,0 +1,22 @@ +module main; + + // 1800-2017 5.7.1 + + // "Unsized unsigned literal constants where the high-order bit is unknown + // (X or x) or three-state (Z or z) shall be extended to the size of the + // expression containing the literal constant." + initial assert (('hx0 | 64'h0) === 64'hxxxx_xxx0); + + initial assert ((1 ? '0 : 16'h0) === 16'h0000); + initial assert ((1 ? '1 : 16'h0) === 16'hffff); + initial assert ((1 ? 'x : 16'h0) === 16'hxxxx); + initial assert ((1 ? 'z : 16'h0) === 16'hzzzz); + + // "All bits of the unsized value shall be set to the value of the specified + // bit." + initial assert ($bits(1 ? '0 : 16'h0) === 16); + initial assert ($bits(1 ? '1 : 16'h0) === 16); + initial assert ($bits(1 ? 'x : 16'h0) === 16); + initial assert ($bits(1 ? 'z : 16'h0) === 16); + +endmodule