From 307d9a69430e7f7f7b43b47356f86729c9b69991 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Sat, 18 Oct 2025 17:38:01 -0700 Subject: [PATCH] Verilog: test for signing casts This tests that signing casts block downwards propagation of expression context. --- regression/verilog/expressions/signing_cast1.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/regression/verilog/expressions/signing_cast1.sv b/regression/verilog/expressions/signing_cast1.sv index 900a57162..610680200 100644 --- a/regression/verilog/expressions/signing_cast1.sv +++ b/regression/verilog/expressions/signing_cast1.sv @@ -11,4 +11,9 @@ module main; // signing casts yield constants parameter Q = signed'(1); + // signing casts block downwards size/type propagation + initial assert (unsigned'(1'b1 + 1'b1) == 0); + initial assert (signed'(1'b1 + 1'b1) == 0); + initial assert ($bits(unsigned'(1'b1 + 1'b1)) == 1); + endmodule