diff --git a/regression/verilog/assignments/assignment-pattern-lhs1.desc b/regression/verilog/assignments/assignment-pattern-lhs1.desc
new file mode 100644
index 000000000..c5d370335
--- /dev/null
+++ b/regression/verilog/assignments/assignment-pattern-lhs1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+assignment-pattern-lhs1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This does not parse.
diff --git a/regression/verilog/assignments/assignment-pattern-lhs1.sv b/regression/verilog/assignments/assignment-pattern-lhs1.sv
new file mode 100644
index 000000000..c30da43cd
--- /dev/null
+++ b/regression/verilog/assignments/assignment-pattern-lhs1.sv
@@ -0,0 +1,16 @@
+module main;
+
+  typedef struct packed {int a, b;} S;
+  S my_s;
+  int x, y;
+
+  initial begin
+    // Assignment pattern on LHS.
+    // Does not parse with Icarus Verilog, VCS, XCelium.
+    // Works with Riviera, Questa.
+    '{x, y} = S'{1, 2};
+
+    assert(x == 1 && y == 2);
+  end
+
+endmodule