From ab3f74c1e34224189e988b9de768dbcbb71d0b60 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sun, 9 Nov 2025 08:10:15 -0800
Subject: [PATCH] SystemVerilog: allow assignment of new to any class type

The new expression has no self-determined type; this allows assignment to
any class type.
---
 regression/verilog/class/new1.desc     | 5 ++---
 src/verilog/verilog_typecheck_expr.cpp | 9 +++++++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/regression/verilog/class/new1.desc b/regression/verilog/class/new1.desc
index 7b532cf15..8682af3e5 100644
--- a/regression/verilog/class/new1.desc
+++ b/regression/verilog/class/new1.desc
@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 new1.sv
 
-^EXIT=0$
+^EXIT=10$
 ^SIGNAL=0$
 --
 --
-The class is not yet recognized as a type.
diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp
index d38a7f4d6..f7de61d08 100644
--- a/src/verilog/verilog_typecheck_expr.cpp
+++ b/src/verilog/verilog_typecheck_expr.cpp
@@ -269,6 +269,15 @@ void verilog_typecheck_exprt::assignment_conversion(
     }
   }
 
+  if(rhs.type().id() == ID_verilog_new)
+  {
+    if(lhs_type.id() == ID_verilog_class_type)
+    {
+      rhs = typecast_exprt{rhs, lhs_type};
+      return;
+    }
+  }
+
   // "The size of the left-hand side of an assignment forms
   // the context for the right-hand expression."