diff --git a/regression/verilog/functioncall/named_parameter_assignment1.desc b/regression/verilog/functioncall/named_parameter_assignment1.desc
new file mode 100644
index 000000000..dcdf9fe90
--- /dev/null
+++ b/regression/verilog/functioncall/named_parameter_assignment1.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+named_parameter_assignment1.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.
diff --git a/regression/verilog/functioncall/named_parameter_assignment1.sv b/regression/verilog/functioncall/named_parameter_assignment1.sv
new file mode 100644
index 000000000..2f2bcfcfa
--- /dev/null
+++ b/regression/verilog/functioncall/named_parameter_assignment1.sv
@@ -0,0 +1,13 @@
+module main;
+
+  function [31:0] my_greater(int a, int b);
+    my_greater = a > b;
+  endfunction
+
+  initial assert(my_greater(2, 1));
+  initial assert(my_greater(.a(2), .b(1)));
+  initial assert(my_greater(2, .b(1)));
+  initial assert(!my_greater(.a(1), .b(2)));
+  initial assert(!my_greater(.b(2), .a(1)));
+
+endmodule