From 63492db1d88cf0744a65935e4fcded2c1aa3602c Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 1 Dec 2025 08:41:36 -0800
Subject: [PATCH] AIG generation: ignore Verilog named blocks

Verilog named blocks do not need to be allocated AIG nodes.
---
 src/trans-netlist/trans_to_netlist.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/trans-netlist/trans_to_netlist.cpp b/src/trans-netlist/trans_to_netlist.cpp
index 7a2f326d9..bdef45e06 100644
--- a/src/trans-netlist/trans_to_netlist.cpp
+++ b/src/trans-netlist/trans_to_netlist.cpp
@@ -229,6 +229,10 @@ void convert_trans_to_netlistt::map_vars(
     {
       return; // ignore modules
     }
+    else if(symbol.type.id() == ID_named_block)
+    {
+      return; // ignore Verilog named blocks
+    }
     else if(symbol.is_type)
       return; // ignore types
     else if (symbol.is_input)