From be9e8e003a6db6ad2efb168c52f7d258f6f74deb Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 1 Dec 2025 18:57:29 -0800
Subject: [PATCH] KNOWNBUG test for SystemVerilog typedefs

Typedefs may depend on module parameters.
---
 regression/verilog/modules/parameters11.desc |  7 +++++++
 regression/verilog/modules/parameters11.sv   | 21 ++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 regression/verilog/modules/parameters11.desc
 create mode 100644 regression/verilog/modules/parameters11.sv

diff --git a/regression/verilog/modules/parameters11.desc b/regression/verilog/modules/parameters11.desc
new file mode 100644
index 000000000..5e2b74235
--- /dev/null
+++ b/regression/verilog/modules/parameters11.desc
@@ -0,0 +1,7 @@
+KNOWNBUG
+parameters11.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/modules/parameters11.sv b/regression/verilog/modules/parameters11.sv
new file mode 100644
index 000000000..6d577d5dc
--- /dev/null
+++ b/regression/verilog/modules/parameters11.sv
@@ -0,0 +1,21 @@
+module my_module;
+
+  parameter some_parameter = 8;
+
+  // typedefs may depend on parameters  
+  typedef bit [some_parameter-1:0] some_type;
+  wire some_type some_wire = -1;
+
+endmodule
+
+module main;
+
+  my_module m8();
+  my_module #(.some_parameter(4)) m4();
+  my_module #(2) m2();
+
+  initial p1: assert (m8.some_wire==255);
+  initial p2: assert (m4.some_wire==15);
+  initial p3: assert (m2.some_wire==3);
+
+endmodule