From ab6b8a18d2da141cfd2e1b2b44799289b644a358 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sun, 10 Mar 2024 16:15:13 -0700
Subject: [PATCH] Verilog: localparam parameter ports

This adds support for localparam parameter ports.
---
 regression/verilog/modules/parameter_ports3.desc |  7 +++++++
 regression/verilog/modules/parameter_ports3.v    | 11 +++++++++++
 src/verilog/parser.y                             |  2 ++
 3 files changed, 20 insertions(+)
 create mode 100644 regression/verilog/modules/parameter_ports3.desc
 create mode 100644 regression/verilog/modules/parameter_ports3.v

diff --git a/regression/verilog/modules/parameter_ports3.desc b/regression/verilog/modules/parameter_ports3.desc
new file mode 100644
index 000000000..ea9781376
--- /dev/null
+++ b/regression/verilog/modules/parameter_ports3.desc
@@ -0,0 +1,7 @@
+CORE
+parameter_ports3.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+The type of the parameter needs to be processed.
diff --git a/regression/verilog/modules/parameter_ports3.v b/regression/verilog/modules/parameter_ports3.v
new file mode 100644
index 000000000..6ffbb2bb7
--- /dev/null
+++ b/regression/verilog/modules/parameter_ports3.v
@@ -0,0 +1,11 @@
+module sub #(parameter p = 1, localparam derived = p+1)();
+
+  always assert p1: derived == 124;
+
+endmodule
+
+module main;
+
+  sub #(123) submodule();
+
+endmodule // main
diff --git a/src/verilog/parser.y b/src/verilog/parser.y
index 2b4718b29..a23c7e7cd 100644
--- a/src/verilog/parser.y
+++ b/src/verilog/parser.y
@@ -1537,6 +1537,8 @@ list_of_variable_identifiers:
 parameter_port_declaration:
           TOK_PARAMETER data_type_or_implicit param_assignment
 		{ $$ = $3; }
+	| TOK_LOCALPARAM data_type_or_implicit param_assignment
+		{ $$ = $3; }
 	| data_type param_assignment
 		{ $$ = $2; }
 	| param_assignment