diff --git a/regression/verilog/expressions/wildcard_equality1.desc b/regression/verilog/expressions/wildcard_equality1.desc
new file mode 100644
index 000000000..6b64197c3
--- /dev/null
+++ b/regression/verilog/expressions/wildcard_equality1.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+wildcard_equality1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Missing SystemVerilog wildcard equality implementation.
diff --git a/regression/verilog/expressions/wildcard_equality1.sv b/regression/verilog/expressions/wildcard_equality1.sv
new file mode 100644
index 000000000..ce7dd02a7
--- /dev/null
+++ b/regression/verilog/expressions/wildcard_equality1.sv
@@ -0,0 +1,16 @@
+module main;
+
+  // wildcard equality operator
+  // 1800-2017 11.4.6
+  property01: assert final ((10==?10)===1);
+  property02: assert final ((10==?20)===0);
+  property03: assert final ((10!=?20)===1);
+  property04: assert final ((10==?20)===0);
+  property05: assert final ((2'b00==?2'b0x)===1);
+  property06: assert final ((2'b10==?2'b0x)===0);
+  property07: assert final ((2'b00!=?2'b0x)===0);
+  property08: assert final ((2'b10!=?2'b0x)===1);
+  property09: assert final ((1'sb1==?2'b11)===0); // zero extension
+  property10: assert final ((1'sb1==?2'sb11)===1); // sign extension
+
+endmodule