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mca-uart.c
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mca-uart.c
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/* mca-uart.c - UART driver for MCA devices.
* Based on sc16is7xx.c, by Jon Ringle <jringle@gridpoint.com>
*
* Copyright (C) 2017-2022 Digi International Inc
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Library General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Library General Public License for more details.
*
* You should have received a copy of the GNU Library General Public
* License along with this library.
*/
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/serial_core.h>
#include <linux/tty_flip.h>
#include <linux/mfd/mca-common/core.h>
#include <linux/delay.h>
#define MCA_BASE_DRVNAME_UART "mca-uart"
#define MCA_UART_DEV_NAME "ttyMCA"
#define MCA_UART_DEFAULT_BRATE 9600
#define MCA_UART_DEFAULT_BAUD_REG MCA_REG_UART_BAUD_9600
#define MCA_UART_MIN_BAUD 1200
#define MCA_UART_MAX_BAUD 230400
#define MCA_UART_RX_FIFO_SIZE 127
#define MCA_UART_TX_FIFO_SIZE 127
#define MCA_UART_CLK 24000000
#define MCA_UART_MAX_TX_FRAME_LEN 32
#define MCA_UART_MAX_RS485_DELAY_MS 250
#define MCA_REG_UART_FLUSH_BUF_MSK (MCA_REG_UART_CFG0_CTX | \
MCA_REG_UART_CFG0_CRX)
#define MCA_UART_HAS_RTS BIT(0)
#define MCA_UART_HAS_CTS BIT(1)
#define MCA_UART_IOS 4
#define MCA_UART_MAX_NUM_UARTS 4
const char *iopins_names[] = {"rx", "tx", "cts", "rts"};
bool required[] = {1, 1, 0, 0};
#define MCA_REG_UART_PIN(p) (MCA_REG_UART_RXPIN + (p))
enum {
WORK_FLUSH_BUF = BIT(0),
WORK_RS485_CFG = BIT(1),
};
struct mca_uart {
u32 line;
struct mca_drv *mca;
struct uart_port port;
struct mutex mutex;
unsigned int baddr;
struct work_struct tx_work;
struct work_struct dc_work;
unsigned int pending_dc_work;
unsigned int has_rtscts;
u8 pins[MCA_UART_IOS];
u8 npins;
bool enable_power_on;
};
struct mca_uart_drv {
int num_uarts;
struct device *dev;
struct mca_drv *mca;
struct device_node *np;
struct uart_driver uart;
struct mca_uart *ports;
};
#define to_mca_uart(p,e) (container_of((p), struct mca_uart, e))
static void mca_uart_stop_tx(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG0,
MCA_REG_UART_CFG0_CTX, MCA_REG_UART_CFG0_CTX);
if (ret)
dev_err(mca_uart->port.dev, "Failed to write MCA_REG_UART_CFG0\n");
}
static void mca_uart_stop_rx(struct uart_port *port)
{
/* Nothing to do here. Shutdown will do the work */
}
static void mca_uart_start_tx(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
if (!work_pending(&mca_uart->tx_work))
schedule_work(&mca_uart->tx_work);
}
static unsigned int mca_uart_tx_empty(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
unsigned int txlvl;
int ret;
ret = regmap_read(regmap, mca_uart->baddr + MCA_REG_UART_TXLVL, &txlvl);
if (ret) {
dev_err(port->dev, "Failed to read MCA_REG_UART_TXLVL\n");
/* This is the behavior if not implemented */
return TIOCSER_TEMT;
}
return (txlvl == MCA_UART_TX_FIFO_SIZE) ? TIOCSER_TEMT : 0;
}
static unsigned int mca_uart_get_mctrl(struct uart_port *port)
{
/*
* DCD and DSR are not wired and CTS/RTS is handled automatically
* so just indicate DSR and CAR asserted. Also regmap cannot be called
* from atomic context, so reading the status of the lines here is not
* possible.
*/
return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
}
static void mca_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
/*
* Regmap cannot be called from atomic context, so this would require a
* work queue to set/clear RTS. However, that line is handled
* automatically by the hardware when using flow control, and the
* get_mctrl for reading CTS and RTS cannot be implemented for the same
* reason. If RTS/CTS are used for something different that hardware
* flow control, perhaps they should be declared as GPIOs.
*/
}
static void mca_uart_break_ctl(struct uart_port *port, int break_state)
{
dev_warn(port->dev, "BREAK condition not supported\n");
}
static void mca_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
unsigned int cfg1 = 0;
unsigned int baudrate;
unsigned int baud_reg_val;
int ret;
/* Mask unsupported termios capabilities */
if (!mca_uart->has_rtscts)
termios->c_cflag &= ~CRTSCTS;
termios->c_iflag &= ~(IXON | IXOFF | IXANY | CMSPAR | CSIZE);
/* Only 8-bit size supported */
termios->c_cflag |= CS8;
if (termios->c_cflag & CSTOPB)
cfg1 |= MCA_REG_UART_CFG1_TWO_STOPBITS;
if (termios->c_cflag & PARENB)
cfg1 |= MCA_REG_UART_CFG1_PARITY_EN;
if (termios->c_cflag & PARODD)
cfg1 |= MCA_REG_UART_CFG1_PARITY_ODD;
if (termios->c_cflag & CRTSCTS) {
if (mca_uart->has_rtscts & MCA_UART_HAS_CTS) {
cfg1 |= MCA_REG_UART_CFG1_CTS_EN;
port->status |= UPSTAT_AUTOCTS;
}
if (mca_uart->has_rtscts & MCA_UART_HAS_RTS) {
cfg1 |= MCA_REG_UART_CFG1_RTS_EN;
port->status |= UPSTAT_AUTORTS;
}
} else {
port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
}
/* Set status ignore mask */
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= MCA_REG_UART_LSR_PARITY_ERROR;
if (termios->c_iflag & IGNBRK)
port->ignore_status_mask |= MCA_REG_UART_LSR_BREAK;
if (!(termios->c_cflag & CREAD))
port->ignore_status_mask |= MCA_REG_UART_LSR_FRAMING_ERROR |
MCA_REG_UART_LSR_PARITY_ERROR |
MCA_REG_UART_LSR_FIFO_OR_ERROR |
MCA_REG_UART_LSR_HW_OR_ERROR |
MCA_REG_UART_LSR_BREAK;
ret = regmap_write(regmap, mca_uart->baddr + MCA_REG_UART_CFG1, cfg1);
if (ret) {
dev_err(port->dev, "Failed to write MCA_REG_UART_CFG1\n");
return;
}
baudrate = uart_get_baud_rate(port, termios, old, MCA_UART_MIN_BAUD,
MCA_UART_MAX_BAUD);
uart_update_timeout(port, termios->c_cflag, baudrate);
switch (baudrate) {
case 1200:
baud_reg_val = MCA_REG_UART_BAUD_1200;
break;
case 2400:
baud_reg_val = MCA_REG_UART_BAUD_2400;
break;
case 4800:
baud_reg_val = MCA_REG_UART_BAUD_4800;
break;
case 9600:
baud_reg_val = MCA_REG_UART_BAUD_9600;
break;
case 19200:
baud_reg_val = MCA_REG_UART_BAUD_19200;
break;
case 38400:
baud_reg_val = MCA_REG_UART_BAUD_38400;
break;
case 57600:
baud_reg_val = MCA_REG_UART_BAUD_57600;
break;
case 115200:
baud_reg_val = MCA_REG_UART_BAUD_115200;
break;
case 230400:
baud_reg_val = MCA_REG_UART_BAUD_230400;
break;
default:
dev_warn(port->dev,
"Baud rate %d not supported, using default %d\n",
baudrate, MCA_UART_DEFAULT_BRATE);
baud_reg_val = MCA_UART_DEFAULT_BAUD_REG;
break;
}
ret = regmap_write(regmap, mca_uart->baddr + MCA_REG_UART_BAUD,
baud_reg_val);
if (ret) {
dev_err(port->dev, "Failed to write MCA_REG_UART_BAUD\n");
return;
}
/* Wait a bit until the uart is reconfigued with the new settings */
msleep(10);
}
static int mca_uart_startup(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
unsigned int cfg_mask;
unsigned int ier_mask;
/* Reset RX and TX FIFOs and enable TX and RX */
cfg_mask = MCA_REG_UART_CFG0_CTX | MCA_REG_UART_CFG0_CRX |
MCA_REG_UART_CFG0_TXEN | MCA_REG_UART_CFG0_RXEN;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG0,
cfg_mask, cfg_mask);
if (ret) {
dev_err(port->dev, "Failed to read MCA_REG_UART_CFG0\n");
return ret;
}
ier_mask = MCA_REG_UART_IER_THR | MCA_REG_UART_IER_RHR |
MCA_REG_UART_IER_RLSE;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_IER,
ier_mask, ier_mask);
if (ret)
dev_err(port->dev, "Failed to read MCA_REG_UART_IER\n");
return ret;
}
static void mca_uart_shutdown(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
unsigned int cfg_mask;
/* Reset RX and TX FIFOs and disable TX and RX */
cfg_mask = MCA_REG_UART_CFG0_CTX | MCA_REG_UART_CFG0_CRX |
MCA_REG_UART_CFG0_TXEN | MCA_REG_UART_CFG0_RXEN;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG0,
cfg_mask,
MCA_REG_UART_CFG0_CTX | MCA_REG_UART_CFG0_CRX);
if (ret)
dev_err(port->dev, "Failed to read MCA_REG_UART_CFG0\n");
/* Disable all IRQs */
ret = regmap_write(regmap, mca_uart->baddr + MCA_REG_UART_IER, 0);
if (ret)
dev_err(port->dev, "Failed to write MCA_REG_UART_IER\n");
}
static const char *mca_uart_type(struct uart_port *port)
{
return "MCA UART";
}
static int mca_uart_request_port(struct uart_port *port)
{
/* Do nothing */
return 0;
}
static void mca_uart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_LPUART;
}
static int mca_uart_verify_port(struct uart_port *port,
struct serial_struct *s)
{
if ((s->type != PORT_UNKNOWN) && (s->type != PORT_LPUART))
return -EINVAL;
if (s->irq != port->irq)
return -EINVAL;
return 0;
}
static void mca_uart_release_port(struct uart_port *port)
{
/* Do nothing */
}
static void mca_uart_throttle(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG1,
MCA_REG_UART_CFG1_THROTTLE,
MCA_REG_UART_CFG1_THROTTLE);
if (ret)
dev_err(port->dev, "Failed to write MCA_REG_UART_CFG1\n");
}
static void mca_uart_unthrottle(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG1,
MCA_REG_UART_CFG1_THROTTLE, 0);
if (ret)
dev_err(port->dev, "Failed to write MCA_REG_UART_CFG1\n");
}
static void mca_uart_flush_buffer(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
mutex_lock(&mca_uart->mutex);
mca_uart->pending_dc_work |= WORK_FLUSH_BUF;
mutex_unlock(&mca_uart->mutex);
schedule_work(&mca_uart->dc_work);
}
static int mca_uart_rs485_config(struct uart_port *port,
struct serial_rs485 *rs485conf)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
if ((rs485conf->delay_rts_before_send > MCA_UART_MAX_RS485_DELAY_MS) ||
(rs485conf->delay_rts_after_send > MCA_UART_MAX_RS485_DELAY_MS))
return -ERANGE;
port->rs485 = *rs485conf;
mutex_lock(&mca_uart->mutex);
mca_uart->pending_dc_work |= WORK_RS485_CFG;
mutex_unlock(&mca_uart->mutex);
schedule_work(&mca_uart->dc_work);
return 0;
}
static const struct uart_ops mca_uart_ops = {
.tx_empty = mca_uart_tx_empty,
.set_mctrl = mca_uart_set_mctrl,
.get_mctrl = mca_uart_get_mctrl,
.stop_tx = mca_uart_stop_tx,
.start_tx = mca_uart_start_tx,
.stop_rx = mca_uart_stop_rx,
.break_ctl = mca_uart_break_ctl,
.startup = mca_uart_startup,
.shutdown = mca_uart_shutdown,
.set_termios = mca_uart_set_termios,
.type = mca_uart_type,
.request_port = mca_uart_request_port,
.release_port = mca_uart_release_port,
.config_port = mca_uart_config_port,
.verify_port = mca_uart_verify_port,
.throttle = mca_uart_throttle,
.unthrottle = mca_uart_unthrottle,
.flush_buffer = mca_uart_flush_buffer,
.pm = NULL,
};
static void mca_uart_handle_tx(struct uart_port *port)
{
struct mca_uart *mca_uart = to_mca_uart(port, port);
struct regmap *regmap = mca_uart->mca->regmap;
struct circ_buf *xmit = &port->state->xmit;
unsigned int to_send;
uint8_t tx_buf[MCA_UART_TX_FIFO_SIZE];
/*
* There is a corner case in which the job is scheduled after the port
* has been shut down and port->state->port.tty is NULL. If not checked,
* uart_tx_stopped() would crash.
*/
if (!port->state->port.tty || uart_circ_empty(xmit) ||
uart_tx_stopped(port))
return;
/* Get length of data pending in circular buffer */
to_send = uart_circ_chars_pending(xmit);
if (likely(to_send)) {
unsigned int txlen;
unsigned int i;
int ret;
/* Limit to size of TX FIFO */
ret = regmap_read(regmap, mca_uart->baddr + MCA_REG_UART_TXLVL,
&txlen);
if (ret) {
dev_err(port->dev,
"Failed to read MCA_REG_UART_TXLVL\n");
txlen = 0;
}
if (unlikely(!txlen)) {
dev_dbg(port->dev, "TX FIFO is full\n");
if (!work_pending(&mca_uart->tx_work))
schedule_work(&mca_uart->tx_work);
return;
}
if (unlikely(txlen > sizeof(tx_buf))) {
dev_err(port->dev,
"Invalid MCA_REG_UART_TXLVL value %d\n", txlen);
if (!work_pending(&mca_uart->tx_work))
schedule_work(&mca_uart->tx_work);
return;
}
if (to_send > txlen)
to_send = txlen;
/*
* Limit the amount of data sent to avoid blocking the bus for
* too long
*/
if (to_send > MCA_UART_MAX_TX_FRAME_LEN)
to_send = MCA_UART_MAX_TX_FRAME_LEN;
port->icount.tx += to_send;
/* Convert to linear buffer */
for (i = 0; i < to_send; ++i) {
tx_buf[i] = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
ret = regmap_bulk_write(regmap,
mca_uart->baddr + MCA_REG_UART_THR,
tx_buf, to_send);
if (ret)
dev_err(port->dev,
"Failed to write MCA_REG_UART_THR\n");
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static void mca_uart_handle_rx(struct mca_uart *mca_uart, u8 iir)
{
struct uart_port *port = &mca_uart->port;
struct regmap *regmap = mca_uart->mca->regmap;
unsigned int flag = TTY_NORMAL;
uint8_t rx_buf[MCA_UART_RX_FIFO_SIZE];
uint8_t error_buf[MCA_UART_RX_FIFO_SIZE];
uint8_t has_errors = iir & MCA_REG_UART_IIR_RLSE;
unsigned int lsr;
unsigned int rxlen;
unsigned int i;
int ret;
ret = regmap_read(regmap, mca_uart->baddr + MCA_REG_UART_RXLVL, &rxlen);
if (ret) {
dev_err(port->dev, "Failed to read MCA_REG_UART_RXLVL\n");
return;
}
if (unlikely(!rxlen))
return;
ret = regmap_bulk_read(regmap, mca_uart->baddr + MCA_REG_UART_RHR,
rx_buf, rxlen);
if (ret) {
dev_warn(port->dev,
"Failed to read MCA_REG_UART_RHR %d, retrying\n", ret);
ret = regmap_bulk_read(regmap,
mca_uart->baddr + MCA_REG_UART_RHR,
rx_buf, rxlen);
if (ret) {
dev_err(port->dev,
"Failed to read MCA_REG_UART_RHR %d\n", ret);
goto exit;
}
}
if (unlikely(has_errors)) {
ret = regmap_read(regmap, mca_uart->baddr + MCA_REG_UART_LSR,
&lsr);
if (ret) {
dev_err(port->dev,
"Failed to read MCA_REG_UART_LSR\n");
return;
}
if (lsr & MCA_REG_UART_LSR_FIFO_OR_ERROR)
dev_warn(port->dev, "fifo overrun\n");
ret = regmap_bulk_read(regmap,
mca_uart->baddr + MCA_REG_UART_RX_ERRORS,
error_buf, rxlen);
if (ret) {
dev_err(port->dev,
"Failed to read MCA_REG_UART_RX_ERRORS\n");
return;
}
}
port->icount.rx += rxlen;
for (i = 0; i < rxlen; i++) {
uint8_t const ch = rx_buf[i];
uint8_t status;
if (unlikely(has_errors)) {
status = error_buf[i];
if (status & MCA_REG_UART_LSR_BREAK) {
port->icount.brk++;
uart_handle_break(port);
} else if (status & MCA_REG_UART_LSR_PARITY_ERROR)
port->icount.parity++;
else if (status & MCA_REG_UART_LSR_FRAMING_ERROR)
port->icount.frame++;
else if (status & MCA_REG_UART_LSR_HW_OR_ERROR)
port->icount.overrun++;
status &= port->read_status_mask;
if (status & MCA_REG_UART_LSR_BREAK)
flag = TTY_BREAK;
else if (status & MCA_REG_UART_LSR_PARITY_ERROR)
flag = TTY_PARITY;
else if (status & MCA_REG_UART_LSR_FRAMING_ERROR)
flag = TTY_FRAME;
else if (status & MCA_REG_UART_LSR_HW_OR_ERROR)
flag = TTY_OVERRUN;
} else {
status = 0;
}
if (uart_handle_sysrq_char(port, ch))
continue;
if (status & port->ignore_status_mask)
continue;
uart_insert_char(port, status, MCA_REG_UART_LSR_HW_OR_ERROR, ch,
flag);
}
exit:
tty_flip_buffer_push(&port->state->port);
}
static irqreturn_t mca_uart_irq_handler(int irq, void *private)
{
struct mca_uart *mca_uart = private;
struct regmap *regmap = mca_uart->mca->regmap;
unsigned int iir;
int ret;
do {
ret = regmap_read(regmap, mca_uart->baddr + MCA_REG_UART_IIR,
&iir);
if (ret) {
dev_err(mca_uart->port.dev,
"Failed to read MCA_REG_UART_IIR\n");
goto ret;
}
if (!iir)
break;
if (iir & MCA_REG_UART_IIR_RHR)
mca_uart_handle_rx(mca_uart, iir);
if (iir & MCA_REG_UART_IIR_THR) {
mutex_lock(&mca_uart->mutex);
mca_uart_handle_tx(&mca_uart->port);
mutex_unlock(&mca_uart->mutex);
}
} while (1);
ret:
return IRQ_HANDLED;
}
static int mca_uart_reconf_rs485(struct mca_uart *mca_uart)
{
struct regmap *regmap = mca_uart->mca->regmap;
struct serial_rs485 *rs485conf = &mca_uart->port.rs485;
unsigned int cfg2_reg = 0;
int ret;
if (rs485conf->flags & SER_RS485_ENABLED)
cfg2_reg |= MCA_REG_UART_CFG2_RS485_EN;
if (!(rs485conf->flags & SER_RS485_RTS_ON_SEND) &&
(rs485conf->flags & SER_RS485_RTS_AFTER_SEND))
cfg2_reg |= MCA_REG_UART_CFG2_RTS_INV;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG2,
MCA_REG_UART_CFG2_RS485_EN |
MCA_REG_UART_CFG2_RTS_INV,
cfg2_reg);
if (ret < 0) {
dev_err(mca_uart->port.dev,
"Failed writing MCA_REG_UART_CFG2 (%d)\n", ret);
return ret;
}
ret = regmap_write(regmap,
mca_uart->baddr + MCA_REG_UART_RS485_PRE_DEL,
rs485conf->delay_rts_before_send);
if (ret) {
dev_err(mca_uart->port.dev,
"Failed writing MCA_REG_UART_RS485_PRE_DEL (%d)\n",
ret);
return ret;
}
ret = regmap_write(regmap,
mca_uart->baddr + MCA_REG_UART_RS485_POST_DEL,
rs485conf->delay_rts_after_send);
if (ret)
dev_err(mca_uart->port.dev,
"Failed writing MCA_UART_RS485_POST_DEL reg (%d)\n",
ret);
return ret;
}
static void mca_uart_dc_work_proc(struct work_struct *ws)
{
struct mca_uart *mca_uart = to_mca_uart(ws, dc_work);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
mutex_lock(&mca_uart->mutex);
if (mca_uart->pending_dc_work & WORK_FLUSH_BUF) {
ret = regmap_update_bits(regmap,
mca_uart->baddr + MCA_REG_UART_CFG0,
MCA_REG_UART_FLUSH_BUF_MSK,
MCA_REG_UART_FLUSH_BUF_MSK);
if (ret)
dev_err(mca_uart->port.dev,
"Failed to read MCA_REG_UART_CFG0\n");
}
if (mca_uart->pending_dc_work & WORK_RS485_CFG)
(void)mca_uart_reconf_rs485(mca_uart);
mca_uart->pending_dc_work = 0;
mutex_unlock(&mca_uart->mutex);
}
static void mca_uart_tx_work_proc(struct work_struct *ws)
{
struct mca_uart *mca_uart = to_mca_uart(ws, tx_work);
mutex_lock(&mca_uart->mutex);
mca_uart_handle_tx(&mca_uart->port);
mutex_unlock(&mca_uart->mutex);
}
static ssize_t power_on_rx_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct tty_port *port = dev_get_drvdata(dev);
struct uart_state *state = container_of(port, struct uart_state, port);
struct uart_port *uart_port = state->uart_port;
struct mca_uart *mca_uart = container_of(uart_port, struct mca_uart,
port);
return sprintf(buf, "%s\n", mca_uart->enable_power_on ?
"enabled" : "disabled");
}
static ssize_t power_on_rx_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct tty_port *port = dev_get_drvdata(dev);
struct uart_state *state = container_of(port, struct uart_state, port);
struct uart_port *uart_port = state->uart_port;
struct mca_uart *mca_uart = container_of(uart_port, struct mca_uart,
port);
struct regmap *regmap = mca_uart->mca->regmap;
int ret;
if (!strncmp(buf, "enabled", sizeof("enabled") - 1))
mca_uart->enable_power_on = true;
else if (!strncmp(buf, "disabled", sizeof("disabled") - 1))
mca_uart->enable_power_on = false;
else
return -EINVAL;
ret = regmap_update_bits(regmap, mca_uart->baddr + MCA_REG_UART_CFG0,
MCA_REG_UART_CFG0_PWR_ON,
mca_uart->enable_power_on ?
MCA_REG_UART_CFG0_PWR_ON : 0);
if (ret < 0)
dev_err(dev, "Failed to write MCA_REG_UART_CFG0\n");
return count;
}
static DEVICE_ATTR(power_on_rx, 0600, power_on_rx_show, power_on_rx_store);
static struct attribute *uart_sysfs_entries[] = {
&dev_attr_power_on_rx.attr,
NULL,
};
static struct attribute_group uart_port_extra_attr = {
.name = "power_extra_opts",
.attrs = uart_sysfs_entries,
};
static const struct of_device_id mca_uart_ids[];
static int mca_uart_get_rs485_config_of(struct mca_uart *mca_uart, struct device_node *np)
{
struct uart_port *port = &mca_uart->port;
struct serial_rs485 *rs485conf = &port->rs485;
u32 rs485_delay[2];
int i;
rs485conf->flags = SER_RS485_RTS_ON_SEND;
if (!of_property_read_u32_array(np, "rs485-rts-delay", rs485_delay, 2)) {
for (i = 0; i < 2; i++) {
if (rs485_delay[i] > MCA_UART_MAX_RS485_DELAY_MS) {
dev_warn(port->dev,
"RS485 rts-%s-send (%u) limit exceeded,"
" set to %d ms\n",
i ? "after" : "before", rs485_delay[i],
MCA_UART_MAX_RS485_DELAY_MS);
rs485_delay[i] = MCA_UART_MAX_RS485_DELAY_MS;
}
}
rs485conf->delay_rts_before_send = rs485_delay[0];
rs485conf->delay_rts_after_send = rs485_delay[1];
}
if (of_property_read_bool(np, "rs485-rts-active-low")) {
rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
}
if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
rs485conf->flags |= SER_RS485_ENABLED;
if (of_property_read_bool(np, "rs485-rx-during-tx"))
rs485conf->flags |= SER_RS485_RX_DURING_TX;
return 0;
}
static int mca_uart_get_pins(struct mca_uart_drv *uart_drv,
struct mca_uart *mca_uart, struct device_node *np)
{
u32 mca_io;
int ret, i, index;
mca_uart->npins = 0;
for (i = 0; i < ARRAY_SIZE(iopins_names); i++) {
index = of_property_match_string(np, "iopins-names",
iopins_names[i]);
if (index < 0) {
if (!required[i])
continue;
dev_err(uart_drv->dev, "Missing '%s' I/O pin name\n",
iopins_names[i]);
return -EINVAL;
}
ret = of_property_read_u32_index(np, "iopins", index, &mca_io);
if (ret < 0 || mca_io >= MCA_MAX_IOS) {
dev_err(uart_drv->dev,
"Missing or invalid I/O pin for '%s'\n",
iopins_names[i]);
return -EINVAL;
}
if (!strcmp(iopins_names[i], "rts"))
mca_uart->has_rtscts |= MCA_UART_HAS_RTS;
if (!strcmp(iopins_names[i], "cts"))
mca_uart->has_rtscts |= MCA_UART_HAS_CTS;
mca_uart->pins[i] = mca_io;
mca_uart->npins++;
}
return 0;
}
#ifdef CONFIG_OF
static int mca_uart_get_config_of(struct mca_uart_drv *uart_drv, int num_uarts)
{
struct device_node *node;
uart_drv->num_uarts = 0;
for_each_child_of_node(uart_drv->np, node) {
struct mca_uart *mca_uart =
&uart_drv->ports[uart_drv->num_uarts];
u32 val;
if (!of_device_is_available(node))
continue;
if (of_property_read_u32(node, "reg", &val)) {
dev_err(uart_drv->dev,
"invalid/missing reg entry in devicetree\n");
continue;
}
mca_uart->baddr = val;
if (of_property_read_u32(node, "index", &val)) {
dev_err(uart_drv->dev,
"invalid/missing index entry in devicetree\n");
continue;
}
mca_uart->line = val;
if (mca_uart_get_pins(uart_drv, mca_uart, node))
continue;
if (mca_uart_get_rs485_config_of(mca_uart, node))
continue;
uart_drv->num_uarts++;
}
if (uart_drv->num_uarts == 0)
return -EINVAL;
return 0;
}
#endif
static int mca_uart_allocate_port_resources(struct mca_uart_drv *uart_drv,
struct mca_uart *mca_uart)
{
struct regmap *regmap = mca_uart->mca->regmap;
int i, ret;
/* wait for the gpio-mca driver until it is initialized */
if (mca_uart->mca->gpio_base == -1)
return -EPROBE_DEFER;
/* Request GPIOs */
for (i = 0; i < mca_uart->npins; i++) {
int mca_io = mca_uart->pins[i];
int gpio = mca_uart->mca->gpio_base + mca_io;
ret = devm_gpio_request(uart_drv->dev, gpio, MCA_BASE_DRVNAME_UART);
if (ret) {
dev_err(uart_drv->dev,
"Failed to allocate MCA IO%d (gpio %d) (%d)\n",
mca_io, gpio, ret);
return ret;
}
ret = regmap_write(regmap,
mca_uart->baddr + MCA_REG_UART_PIN(i),
mca_io);
if (ret) {
dev_err(uart_drv->dev,
"Failed to write MCA UART IO %d (%d)\n",
mca_io, ret);
return ret;
}
}
/* Request interrupt */
ret = devm_request_threaded_irq(uart_drv->dev,
mca_uart->port.irq,
NULL, mca_uart_irq_handler,
IRQF_ONESHOT, MCA_BASE_DRVNAME_UART,
mca_uart);
if (ret) {
dev_err(uart_drv->dev, "Failed to register IRQ\n");
goto error_ios;
}
return 0;
error_ios:
for (i = 0; i < mca_uart->npins; i++) {
int io = mca_uart->pins[i];
devm_gpio_free(uart_drv->dev, uart_drv->mca->gpio_base + io);
}
return ret;
}
static int mca_uart_release_port_resources(struct mca_uart *mca_uart)
{
struct mca_uart_drv *uart_drv =
dev_get_drvdata(mca_uart->port.dev->parent);
int i;
cancel_work_sync(&mca_uart->tx_work);
cancel_work_sync(&mca_uart->dc_work);
mutex_destroy(&mca_uart->mutex);
uart_remove_one_port(&uart_drv->uart, &mca_uart->port);
if (mca_uart->port.irq)
devm_free_irq(uart_drv->dev, mca_uart->port.irq, mca_uart);
for (i = 0; i < mca_uart->npins; i++) {
int io = mca_uart->pins[i];
devm_gpio_free(uart_drv->dev, uart_drv->mca->gpio_base + io);
}
return 0;
}
static int mca_uart_probe(struct platform_device *pdev)
{
struct mca_drv *mca = dev_get_drvdata(pdev->dev.parent);
struct regmap *regmap = mca->regmap;
struct mca_uart_drv *uart_drv;
struct device_node *np;
u32 num_uarts;
int ret, i, pin;
char msg[256];
if (IS_ERR(mca))
return PTR_ERR(mca);
/* Find entry in device-tree */
if (!mca->dev->of_node)
return -ENODEV;
/* Return if not enabled in the device-tree */
np = of_find_matching_node(NULL, mca_uart_ids);
if (!np || !of_device_is_available(np)) {
of_node_put(np);
return -ENODEV;
}