Respect FP bit in MSR when running floating point instructions - #135
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Rather than running them normally, they should trigger a "no FPU" exception. This appears to be required to allow correct graphical rendering under Mac OS X - the FP bit cleared via mtmsr and rfi instructions and something else appears to be relying on the exception to be thrown. Implemented by maintaining a parallel version of the OpcodeGrabber table (OpcodeGrabberNoFPU) which contains alternate implementations for all the floating point instructions. We switch the table whenever the MSR value changes. This should minimize the overhead of doing these checks.
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mihaip
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In dingusdev#135 we switched from a static OpcodeGrabber table to a curOpcodeGrabber pointer in ppc_main_opcode results. This results in an extra indirection (as far as generated assembly having an additional load), which reduces execution speed. Switch to making the opcode grabber into a parameter to ppc_main_opcode, and make ppc_exec_inner keep it up to date (via an EXEF_OPCODE exception flag). Also fixes FPU instructions in ppctestss - we now need to set the FP MSR bit when initializing the CPU.
mihaip
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Jan 26, 2025
In dingusdev#135 we switched from a static OpcodeGrabber table to a curOpcodeGrabber pointer in ppc_main_opcode. This results in an extra indirection (as far as generated assembly having an additional load), which reduces execution speed. Switch to making the opcode grabber into a parameter to ppc_main_opcode, and make ppc_exec_inner keep it up to date (via an EXEF_OPCODE exception flag). Also fixes FPU instructions in ppctests - we now need to set the FP MSR bit when initializing the CPU.
mihaip
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Jan 27, 2025
To make them throw NO_FPU exceptions when the MSR FP bit is not set, we switch between two different opcode tables (using the same approach as dingusdev/dingusppc#135 and dingusdev/dingusppc#136) Should be a no-op to a slight regression in the benchmark (since it has no FPU instructions and there's the slight overhead of checking for MSR changes), but instead it goes from ~442.5 to 460 MiB/s. ¯\_(ツ)_/¯
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Rather than running them normally, they should trigger a "no FPU" exception. This appears to be required to allow correct graphical rendering under Mac OS X - the FP bit cleared via
mtmsrandrfiinstructions and something else appears to be relying on the exception to be thrown.Implemented by maintaining a parallel version of the
OpcodeGrabbertable (OpcodeGrabberNoFPU) which contains alternate implementations for all the floating point instructions. We switch the table whenever the MSR value changes. This should minimize the overhead of doing these checks.