Mitigate performance impact of respecting FP bit#136
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Initial MSR state is CPU dependent. We need to account for that.
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In dingusdev#135 we switched from a static OpcodeGrabber table to a curOpcodeGrabber pointer in ppc_main_opcode. This results in an extra indirection (as far as generated assembly having an additional load), which reduces execution speed. Switch to making the opcode grabber into a parameter to ppc_main_opcode, and make ppc_exec_inner keep it up to date (via an EXEF_OPCODE exception flag). Also fixes FPU instructions in ppctests - we now need to set the FP MSR bit when initializing the CPU.
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@maximumspatium OK, redid this to not make any assumptions about the initial state of the MSR field. Also fixed ppctests. |
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To make them throw NO_FPU exceptions when the MSR FP bit is not set, we switch between two different opcode tables (using the same approach as dingusdev/dingusppc#135 and dingusdev/dingusppc#136) Should be a no-op to a slight regression in the benchmark (since it has no FPU instructions and there's the slight overhead of checking for MSR changes), but instead it goes from ~442.5 to 460 MiB/s. ¯\_(ツ)_/¯
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In #135 we switched from a static
OpcodeGrabbertable to acurOpcodeGrabberpointer inppc_main_opcode. This results in an extra indirection (as far as generated assembly having an additional load), which reduces execution speed.Switch to making the opcode grabber into a parameter to
ppc_main_opcode, and makeppc_exec_innerkeep it up to date (via anEXEF_OPCODEexception flag).Also fixes FPU instructions in
ppctests- we now need to set the FP MSR bit when initializing the CPU.