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  1. This is my first trial project for designing RISC-V in Chisel

    Scala 10

  2. fpga simulation and synthesis for scr1 which designed by syntacore

    1

  3. Repository for learning Chisel3

    Scala 2

  4. Forked from syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog

412 contributions in the last year

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Contribution activity

December 2019

diningyo has no activity yet for this period.

November 2019

2 contributions in private repositories Nov 27

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