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Add option to compile for riscv64imac CPU targets

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diodesign committed Jul 5, 2019
1 parent 333f6d2 commit 6aa90b5e0efc244babfe1c278053607fd5b63541
Showing with 35 additions and 6 deletions.
  1. +10 −4 .cargo/config
  2. +4 −0 .travis.yml
  3. +3 −0 BUILDING.md
  4. +6 −0 Cargo.toml
  5. +9 −0 build.rs
  6. +3 −2 src/platform/riscv/src/physmem.rs
@@ -1,15 +1,21 @@
# set a default build triple
[build]
target = "riscv64gc-unknown-none-elf"
target = "riscv32imac-unknown-none-elf"

# Find the linker for 32-bit RISC-V targets
# Find the linker for 32-bit RISC-V (IMAC) targets
[target.riscv32imac-unknown-none-elf]
rustflags = [ "-Z", "pre-link-arg=-nostartfiles", "-C", "link-arg=-Tsrc/platform/riscv/link.ld" ]
linker = "riscv32-elf-ld"
ar = "riscv32-elf-ar"

# Find the linker for 64-bit RISC-V targets
[target.riscv64gc-unknown-none-elf]
# Find the linker for 64-bit RISC-V (IMAC) targets
[target.riscv64imac-unknown-none-elf]
rustflags = [ "-Z", "pre-link-arg=-nostartfiles", "-C", "link-arg=-Tsrc/platform/riscv/link.ld" ]
linker = "riscv64-elf-ld"
ar = "riscv64-elf-ar"

# Find the linker for 64-bit RISC-V (GC) targets
[target.riscv64gc-unknown-none-elf]
rustflags = [ "-Z", "pre-link-arg=-nostartfiles", "-C", "link-arg=-Tsrc/platform/riscv/link.ld" ]
linker = "riscv64-elf-ld"
ar = "riscv64-elf-ar"
@@ -7,6 +7,8 @@ language: rust
rust:
- nightly
cache: cargo
notifications:
email: false

install:
- sudo apt-get -qq update
@@ -27,10 +29,12 @@ install:

before_script:
rustup target install riscv32imac-unknown-none-elf
rustup target install riscv64imac-unknown-none-elf
rustup target install riscv64gc-unknown-none-elf

script:
- cargo build --target riscv32imac-unknown-none-elf
- cargo build --target riscv64imac-unknown-none-elf
- cargo build --target riscv64gc-unknown-none-elf

branches:
@@ -35,6 +35,8 @@ cd
rustup toolchain install nightly
rustup default nightly
rustup target install riscv32imac-unknown-none-elf
rustup target install riscv64imac-unknown-none-elf
rustup target install riscv64gc-unknown-none-elf
```

You're almost ready to build diosix. Next, to make sure your paths are always set up to find Rust and Cargo, add two lines
@@ -70,6 +72,7 @@ defining the required CPU architecture, in the form:

So far, diosix supports the following CPU architure targets:
* `riscv32imac-unknown-none-elf`
* `riscv64imac-unknown-none-elf`
* `riscv64gc-unknown-none-elf`

Once built, the compiled kernel executable can be found in `target/<CPU architecture>/release/kernel` for the given
@@ -36,6 +36,12 @@ lazy_static = { path = "src/contrib/lazy-static.rs" }
spin = { path = "src/contrib/spin-rs" }
hashmap_core = { path = "src/contrib/hashmap_core" }

[target.riscv64imac-unknown-none-elf.dependencies]
platform = { path = "src/platform/riscv/" }
lazy_static = { path = "src/contrib/lazy-static.rs" }
spin = { path = "src/contrib/spin-rs" }
hashmap_core = { path = "src/contrib/hashmap_core" }

[target.riscv64gc-unknown-none-elf.dependencies]
platform = { path = "src/platform/riscv/" }
lazy_static = { path = "src/contrib/lazy-static.rs" }
@@ -15,6 +15,7 @@
Acceptable targets:
* riscv32imac-unknown-none-elf
* riscv64imac-unknown-none-elf
* riscv64gc-unknown-none-elf
eg: cargo build --target riscv32imac-unknown-none-elf
@@ -54,6 +55,14 @@ impl Target
width: 32,
abi: String::from("ilp32")
},
"riscv64imac" => Target
{
cpu_arch: String::from("rv64imac"),
gnu_prefix: String::from("riscv64"),
platform: String::from("riscv"),
width: 64,
abi: String::from("lp64")
},
"riscv64gc" => Target
{
cpu_arch: String::from("rv64gc"),
@@ -97,7 +97,7 @@ impl Iterator for RAMAreaIter
self.pos = self.kernel_area.base + self.kernel_area.size as PhysMemBase;
}

/* determine whether we're outside a kernel area */
/* determine whether we're below the kernel area */
if self.pos < self.kernel_area.base
{
/* we're below the kernel: round up from wherever we are to the kernel area base */
@@ -111,9 +111,10 @@ impl Iterator for RAMAreaIter
return Some(area);
}

/* or if we're above or in the kernel area */
if self.pos >= self.kernel_area.base + self.kernel_area.size as PhysMemBase
{
/* we're clear of the kernel round up to end of ram */
/* we're clear of the kernel, so round up to end of ram */
let area = RAMArea
{
base: self.pos,

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