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Port to ARM hardfloat ABI.

This port is almost entirely taken from the source code release by
SCEI available at http://www.scei.co.jp/psvita-license/mono.html

Whilst the relevant files in this diff don't have updated copyright
headers (not uncommon for vendor changes), it's reasonable to assume
that some or all of the code in question is ©2011-2012, either to
SCEI or one of its subsidiaries such as SCEA. Other files in the vendor
tree say SCEA, anyway.
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1 parent 8c20f9a commit 3a28afb60e21428dc6a773aaed5153f0dbef4f28 @directhex committed Aug 19, 2012
Showing with 549 additions and 142 deletions.
  1. +13 −6 configure.in
  2. +6 −0 mono/arch/arm/arm-vfp-codegen.h
  3. +28 −20 mono/mini/cpu-arm.md
  4. +458 −103 mono/mini/mini-arm.c
  5. +16 −5 mono/mini/mini-arm.h
  6. +3 −0 mono/mini/mini-ops.h
  7. +3 −0 mono/mini/mini.h
  8. +22 −8 mono/mini/tramp-arm.c
View
@@ -2663,12 +2663,19 @@ if test ${TARGET} = ARM && test x$cross_compiling = xno && test x$enable_mcs_bui
dnl ******************************************
AC_MSG_CHECKING(which FPU to use)
- ORIG_CFLAGS=$CFLAGS
- CFLAGS="$CFLAGS -mfpu=vfp -mfloat-abi=softfp"
- AC_TRY_RUN([
- int main () { __asm__ ("faddd d7, d6, d7"); return 0; }
- ], fpu=VFP, fpu=NONE)
- CFLAGS=$ORIG_CFLAGS
+ fpu=NONE
+ if gcc -v 2>&1 | grep -q -- '--with-float=hard'; then
+ fpu=VFP_HARD
+ fi
+
+ if test x$fpu = xNONE; then
+ ORIG_CFLAGS=$CFLAGS
+ CFLAGS="$CFLAGS -mfpu=vfp -mfloat-abi=softfp"
+ AC_TRY_RUN([
+ int main () { __asm__ ("faddd d7, d6, d7"); return 0; }
+ ], fpu=VFP, fpu=NONE)
+ CFLAGS=$ORIG_CFLAGS
+ fi
if test x$fpu = xNONE; then
AC_TRY_COMPILE([], [
@@ -156,6 +156,12 @@ enum {
#define ARM_FSTD(p,freg,base,offset) \
ARM_FSTD_COND(p,freg,base,offset,ARMCOND_AL)
+/* VSTM/VLDM */
+#define VSTMIA_COND(p,cond,rn,w,first_reg,nregs) ARM_EMIT((p), ((nregs * 2) << 0) | (0xb << 8) | (((first_reg) & 0xf) << 12) | ((rn) << 16) | (0 << 20) | ((w) << 21) | ((first_reg >> 4) << 22) | (1 << 23) | (0 << 24) | (0x6 << 25) | ((cond) << 28))
+#define VSTMIA(p,rn,w,first_reg,nregs) VSTMIA_COND((p), ARMCOND_AL, (rn), (w), (first_reg), (nregs))
+#define VLDMIA_COND(p,cond,rn,w,first_reg,nregs) ARM_EMIT((p), ((nregs * 2) << 0) | (0xb << 8) | (((first_reg) & 0xf) << 12) | ((rn) << 16) | (1 << 20) | ((w) << 21) | ((first_reg >> 4) << 22) | (1 << 23) | (0 << 24) | (0x6 << 25) | ((cond) << 28))
+#define VLDMIA(p,rn,w,first_reg,nregs) VLDMIA_COND((p), ARMCOND_AL, (rn), (w), (first_reg), (nregs))
+
#include "arm_vfpmacros.h"
/* coprocessor register transfer */
View
@@ -77,21 +77,24 @@ fcompare: src1:f src2:f len:12
oparglist: src1:i len:12
setlret: src1:i src2:i len:12
checkthis: src1:b len:4
-call: dest:a clob:c len:20
-call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:12 clob:c
-voidcall: len:20 clob:c
-voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:12 clob:c
-fcall: dest:g len:28 clob:c
-fcall_reg: dest:g src1:i len:16 clob:c
-fcall_membase: dest:g src1:b len:20 clob:c
-lcall: dest:l len:20 clob:c
-lcall_reg: dest:l src1:i len:8 clob:c
-lcall_membase: dest:l src1:b len:12 clob:c
-vcall: len:20 clob:c
-vcall_reg: src1:i len:8 clob:c
-vcall_membase: src1:b len:12 clob:c
+call: dest:a clob:c len:84
+call_reg: dest:a src1:i len:100 clob:c
+call_membase: dest:a src1:b len:100 clob:c
+voidcall: len:100 clob:c
+voidcall_reg: src1:i len:100 clob:c
+voidcall_membase: src1:b len:100 clob:c
+fcall: dest:g len:128 clob:c
+fcall_reg: dest:g src1:i len:100 clob:c
+fcall_membase: dest:g src1:b len:100 clob:c
+lcall: dest:l len:100 clob:c
+lcall_reg: dest:l src1:i len:100 clob:c
+lcall_membase: dest:l src1:b len:100 clob:c
+vcall: len:110 clob:c
+
+vcall_reg: src1:i len:110 clob:c
+
+vcall_membase: src1:b len:110 clob:c
+
iconst: dest:i len:16
r4const: dest:f len:24
r8const: dest:f len:20
@@ -122,6 +125,8 @@ loadu4_membase: dest:i src1:b len:4
loadi8_membase: dest:i src1:b
loadr4_membase: dest:f src1:b len:8
loadr8_membase: dest:f src1:b len:24
+arm_loadr4_membase: dest:f src1:b len:8
+
load_memindex: dest:i src1:b src2:i len:4
loadi1_memindex: dest:i src1:b src2:i len:4
loadu1_memindex: dest:i src1:b src2:i len:4
@@ -204,7 +209,7 @@ sbb_imm: dest:i src1:i len:12
br_reg: src1:i len:8
bigmul: len:8 dest:l src1:i src2:i
bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:8 dest:i clob:c
+tls_get: len:12 dest:i clob:c
# 32 bit opcodes
int_add: dest:i src1:i src2:i len:4
@@ -308,10 +313,10 @@ icompare_imm: src1:i len:12
long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
-vcall2: len:20 clob:c
-vcall2_reg: src1:i len:8 clob:c
-vcall2_membase: src1:b len:12 clob:c
-dyn_call: src1:i src2:i len:120 clob:c
+vcall2: len:40 clob:c
+vcall2_reg: src1:i len:28 clob:c
+vcall2_membase: src1:b len:32 clob:c
+dyn_call: src1:i src2:i len:128 clob:c
# This is different from the original JIT opcodes
float_beq: len:20
@@ -331,3 +336,6 @@ gc_liveness_def: len:0
gc_liveness_use: len:0
gc_spill_slot_liveness_def: len:0
gc_param_slot_liveness_def: len:0
+
+arm_outarg_vfp_r4: dest:f src1:f len:16
+
Oops, something went wrong. Retry.

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