anv: implement missing PIPE_CONTROL restriction in GPGPU

I saw this programming note a while ago but never sent the patch...
/o\

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109020

Author: llandwerlin-intel

src/intel/vulkan/genX_cmd_buffer.c

@@ -177,6 +177,18 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
       pc.TextureCacheInvalidationEnable = true;
       pc.ConstantCacheInvalidationEnable = true;
       pc.StateCacheInvalidationEnable = true;
+
+      /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
+       *
+       *    Project: SKL+
+       *
+       *    "“CS Stall” bit in PIPE_CONTROL command must be always set for
+       *    GPGPU workloads when “Texture Cache Invalidation Enable” bit is
+       *    set"
+       */
+#if GEN_GEN >= 9
+      pc.CommandStreamerStallEnable = cmd_buffer->state.current_pipeline == GPGPU;
+#endif
    }
 }
 
@@ -1599,6 +1611,18 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
       pc.InstructionCacheInvalidateEnable = true;
       pc.StateCacheInvalidationEnable = true;
       pc.PostSyncOperation = NoWrite;
+
+      /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
+       *
+       *    Project: SKL+
+       *
+       *    "“CS Stall” bit in PIPE_CONTROL command must be always set for
+       *    GPGPU workloads when “Texture Cache Invalidation Enable” bit is
+       *    set"
+       */
+#if GEN_GEN >= 9
+      pc.CommandStreamerStallEnable = cmd_buffer->state.current_pipeline == GPGPU;
+#endif
    }
 
    /* Now send a third stalling flush to make sure that invalidation is
@@ -1801,6 +1825,20 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
          pipe.InstructionCacheInvalidateEnable =
             bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
 
+         /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
+          *
+          *    Project: SKL+
+          *
+          *    "“CS Stall” bit in PIPE_CONTROL command must be always set for
+          *    GPGPU workloads when “Texture Cache Invalidation Enable” bit is
+          *    set"
+          */
+#if GEN_GEN >= 9
+         pipe.CommandStreamerStallEnable =
+            cmd_buffer->state.current_pipeline == GPGPU &&
+            (bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT);
+#endif
+
          /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
           *
           *    "When VF Cache Invalidate is set “Post Sync Operation” must be
@@ -3366,6 +3404,18 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
       pc.StateCacheInvalidationEnable     = true;
       pc.InstructionCacheInvalidateEnable = true;
       pc.PostSyncOperation                = NoWrite;
+
+      /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
+       *
+       *    Project: SKL+
+       *
+       *    "“CS Stall” bit in PIPE_CONTROL command must be always set for
+       *    GPGPU workloads when “Texture Cache Invalidation Enable” bit is
+       *    set"
+       */
+#if GEN_GEN >= 9
+      pc.CommandStreamerStallEnable = cmd_buffer->state.current_pipeline == GPGPU;
+#endif
    }
 
    anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {