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cod1.d
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cod1.d
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/**
* Compiler implementation of the
* $(LINK2 http://www.dlang.org, D programming language).
*
* Copyright: Copyright (C) 1984-1998 by Symantec
* Copyright (C) 2000-2018 by The D Language Foundation, All Rights Reserved
* Authors: $(LINK2 http://www.digitalmars.com, Walter Bright)
* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
* Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/backend/cod1.d, backend/cod1.d)
* Coverage: https://codecov.io/gh/dlang/dmd/src/master/src/dmd/backend/cod1.d
*/
module dmd.backend.cod1;
version (SCPP)
version = COMPILE;
version (MARS)
version = COMPILE;
version (COMPILE)
{
import core.stdc.stdio;
import core.stdc.stdlib;
import core.stdc.string;
import dmd.backend.cc;
import dmd.backend.cdef;
import dmd.backend.code;
import dmd.backend.code_x86;
import dmd.backend.codebuilder;
import dmd.backend.memh;
import dmd.backend.el;
import dmd.backend.exh;
import dmd.backend.global;
import dmd.backend.obj;
import dmd.backend.oper;
import dmd.backend.rtlsym;
import dmd.backend.ty;
import dmd.backend.type;
import dmd.backend.xmm;
extern (C++):
int REGSIZE();
extern __gshared CGstate cgstate;
extern __gshared ubyte[FLMAX] segfl, stackfl;
private extern (D) uint mask(uint m) { return 1 << m; }
private void genorreg(ref CodeBuilder c, uint t, uint f) { genregs(c, 0x09, f, t); }
/* array to convert from index register to r/m field */
/* AX CX DX BX SP BP SI DI */
private __gshared const byte[8] regtorm32 = [ 0, 1, 2, 3,-1, 5, 6, 7 ];
__gshared const byte[8] regtorm = [ -1,-1,-1, 7,-1, 6, 4, 5 ];
targ_size_t paramsize(elem *e, tym_t tyf);
//void funccall(ref CodeBuilder cdb,elem *e,uint numpara,uint numalign,
// regm_t *pretregs,regm_t keepmsk, bool usefuncarg);
/**************************
* Determine if e is a 32 bit scaled index addressing mode.
* Returns:
* 0 not a scaled index addressing mode
* !=0 the value for ss in the SIB byte
*/
int isscaledindex(elem *e)
{
targ_uns ss;
assert(!I16);
while (e.Eoper == OPcomma)
e = e.EV.E2;
if (!(e.Eoper == OPshl && !e.Ecount &&
e.EV.E2.Eoper == OPconst &&
(ss = e.EV.E2.EV.Vuns) <= 3
)
)
ss = 0;
return ss;
}
/*********************************************
* Generate code for which isscaledindex(e) returned a non-zero result.
*/
/*private*/ void cdisscaledindex(ref CodeBuilder cdb,elem *e,regm_t *pidxregs,regm_t keepmsk)
{
// Load index register with result of e.EV.E1
while (e.Eoper == OPcomma)
{
regm_t r = 0;
scodelem(cdb, e.EV.E1, &r, keepmsk, true);
freenode(e);
e = e.EV.E2;
}
assert(e.Eoper == OPshl);
scodelem(cdb, e.EV.E1, pidxregs, keepmsk, true);
freenode(e.EV.E2);
freenode(e);
}
/***********************************
* Determine index if we can do two LEA instructions as a multiply.
* Returns:
* 0 can't do it
*/
enum
{
SSFLnobp = 1, /// can't have EBP in relconst
SSFLnobase1 = 2, /// no base register for first LEA
SSFLnobase = 4, /// no base register
SSFLlea = 8, /// can do it in one LEA
}
struct Ssindex
{
targ_uns product;
ubyte ss1;
ubyte ss2;
ubyte ssflags; /// SSFLxxxx
}
private __gshared const Ssindex[21] ssindex_array =
[
{ 0, 0, 0 }, // [0] is a place holder
{ 3, 1, 0, SSFLnobp | SSFLlea },
{ 5, 2, 0, SSFLnobp | SSFLlea },
{ 9, 3, 0, SSFLnobp | SSFLlea },
{ 6, 1, 1, SSFLnobase },
{ 12, 1, 2, SSFLnobase },
{ 24, 1, 3, SSFLnobase },
{ 10, 2, 1, SSFLnobase },
{ 20, 2, 2, SSFLnobase },
{ 40, 2, 3, SSFLnobase },
{ 18, 3, 1, SSFLnobase },
{ 36, 3, 2, SSFLnobase },
{ 72, 3, 3, SSFLnobase },
{ 15, 2, 1, SSFLnobp },
{ 25, 2, 2, SSFLnobp },
{ 27, 3, 1, SSFLnobp },
{ 45, 3, 2, SSFLnobp },
{ 81, 3, 3, SSFLnobp },
{ 16, 3, 1, SSFLnobase1 | SSFLnobase },
{ 32, 3, 2, SSFLnobase1 | SSFLnobase },
{ 64, 3, 3, SSFLnobase1 | SSFLnobase },
];
int ssindex(int op,targ_uns product)
{
if (op == OPshl)
product = 1 << product;
for (size_t i = 1; i < ssindex_array.length; i++)
{
if (ssindex_array[i].product == product)
return cast(int)i;
}
return 0;
}
/***************************************
* Build an EA of the form disp[base][index*scale].
* Input:
* c struct to fill in
* base base register (-1 if none)
* index index register (-1 if none)
* scale scale factor - 1,2,4,8
* disp displacement
*/
void buildEA(code *c,int base,int index,int scale,targ_size_t disp)
{
ubyte rm;
ubyte sib;
ubyte rex = 0;
sib = 0;
if (!I16)
{ uint ss;
assert(index != SP);
switch (scale)
{ case 1: ss = 0; break;
case 2: ss = 1; break;
case 4: ss = 2; break;
case 8: ss = 3; break;
default: assert(0);
}
if (base == -1)
{
if (index == -1)
rm = modregrm(0,0,5);
else
{
rm = modregrm(0,0,4);
sib = modregrm(ss,index & 7,5);
if (index & 8)
rex |= REX_X;
}
}
else if (index == -1)
{
if (base == SP)
{
rm = modregrm(2, 0, 4);
sib = modregrm(0, 4, SP);
}
else
{ rm = modregrm(2, 0, base & 7);
if (base & 8)
{ rex |= REX_B;
if (base == R12)
{
rm = modregrm(2, 0, 4);
sib = modregrm(0, 4, 4);
}
}
}
}
else
{
rm = modregrm(2, 0, 4);
sib = modregrm(ss,index & 7,base & 7);
if (index & 8)
rex |= REX_X;
if (base & 8)
rex |= REX_B;
}
}
else
{
// -1 AX CX DX BX SP BP SI DI
static immutable ubyte[9][9] EA16rm =
[
[ 0x06,0x09,0x09,0x09,0x87,0x09,0x86,0x84,0x85, ], // -1
[ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, ], // AX
[ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, ], // CX
[ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, ], // DX
[ 0x87,0x09,0x09,0x09,0x09,0x09,0x09,0x80,0x81, ], // BX
[ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, ], // SP
[ 0x86,0x09,0x09,0x09,0x09,0x09,0x09,0x82,0x83, ], // BP
[ 0x84,0x09,0x09,0x09,0x80,0x09,0x82,0x09,0x09, ], // SI
[ 0x85,0x09,0x09,0x09,0x81,0x09,0x83,0x09,0x09, ] // DI
];
assert(scale == 1);
rm = EA16rm[base + 1][index + 1];
assert(rm != 9);
}
c.Irm = rm;
c.Isib = sib;
c.Irex = rex;
c.IFL1 = FLconst;
c.IEV1.Vuns = cast(targ_uns)disp;
}
/*********************************************
* Build REX, modregrm and sib bytes
*/
uint buildModregrm(int mod, int reg, int rm)
{
uint m;
if (I16)
m = modregrm(mod, reg, rm);
else
{
if ((rm & 7) == SP && mod != 3)
m = (modregrm(0,4,SP) << 8) | modregrm(mod,reg & 7,4);
else
m = modregrm(mod,reg & 7,rm & 7);
if (reg & 8)
m |= REX_R << 16;
if (rm & 8)
m |= REX_B << 16;
}
return m;
}
/****************************************
* Generate code for eecontext
*/
void genEEcode()
{
CodeBuilder cdb;
cdb.ctor();
eecontext.EEin++;
regcon.immed.mval = 0;
regm_t retregs = 0; //regmask(eecontext.EEelem.Ety);
assert(EEStack.offset >= REGSIZE);
cod3_stackadj(cdb, cast(int)(EEStack.offset - REGSIZE));
cdb.gen1(0x50 + SI); // PUSH ESI
cdb.genadjesp(cast(int)EEStack.offset);
gencodelem(cdb, eecontext.EEelem, &retregs, false);
code *c = cdb.finish();
assignaddrc(c);
pinholeopt(c,null);
jmpaddr(c);
eecontext.EEcode = gen1(c, 0xCC); // INT 3
eecontext.EEin--;
}
/********************************************
* Gen a save/restore sequence for mask of registers.
* Params:
* regm = mask of registers to save
* cdbsave = save code appended here
* cdbrestore = restore code appended here
* Returns:
* amount of stack consumed
*/
uint gensaverestore(regm_t regm,ref CodeBuilder cdbsave,ref CodeBuilder cdbrestore)
{
//printf("gensaverestore2(%s)\n", regm_str(regm));
regm &= mBP | mES | ALLREGS | XMMREGS | mST0 | mST01;
if (!regm)
return 0;
uint stackused = 0;
code *[regm.sizeof * 8] restore;
int i;
for (i = 0; regm; i++)
{
if (regm & 1)
{
code *cs2;
if (i == ES)
{
stackused += REGSIZE;
cdbsave.gen1(0x06); // PUSH ES
cs2 = gen1(null, 0x07); // POP ES
}
else if (i == ST0 || i == ST01)
{
CodeBuilder cdb;
cdb.ctor();
gensaverestore87(1 << i, cdbsave, cdb);
cs2 = cdb.finish();
}
else if (i >= XMM0 || I64 || cgstate.funcarg.size)
{ uint idx;
regsave.save(cdbsave, i, &idx);
CodeBuilder cdb;
cdb.ctor();
regsave.restore(cdb, i, idx);
cs2 = cdb.finish();
}
else
{
stackused += REGSIZE;
cdbsave.gen1(0x50 + (i & 7)); // PUSH i
cs2 = gen1(null, 0x58 + (i & 7)); // POP i
if (i & 8)
{ code_orrex(cdbsave.last(), REX_B);
code_orrex(cs2, REX_B);
}
}
restore[i] = cs2;
}
else
restore[i] = null;
regm >>= 1;
}
while (i)
{
code *c = restore[--i];
if (c)
{
cdbrestore.append(c);
}
}
return stackused;
}
/****************************************
* Clean parameters off stack.
* Input:
* numpara amount to adjust stack pointer
* keepmsk mask of registers to not destroy
*/
void genstackclean(ref CodeBuilder cdb,uint numpara,regm_t keepmsk)
{
//dbg_printf("genstackclean(numpara = %d, stackclean = %d)\n",numpara,cgstate.stackclean);
if (numpara && (cgstate.stackclean || STACKALIGN == 16))
{
/+
if (0 && // won't work if operand of scodelem
numpara == stackpush && // if this is all those pushed
needframe && // and there will be a BP
!config.windows &&
!(regcon.mvar & fregsaved) // and no registers will be pushed
)
genregs(cdb,0x89,BP,SP); // MOV SP,BP
else
+/
{
regm_t scratchm = 0;
if (numpara == REGSIZE && config.flags4 & CFG4space)
{
scratchm = ALLREGS & ~keepmsk & regcon.used & ~regcon.mvar;
}
if (scratchm)
{
uint r;
allocreg(cdb, &scratchm, &r, TYint);
cdb.gen1(0x58 + r); // POP r
}
else
cod3_stackadj(cdb, -numpara);
}
stackpush -= numpara;
cdb.genadjesp(-numpara);
}
}
/*********************************
* Generate code for a logical expression.
* Input:
* e elem
* jcond
* bit 1 if true then goto jump address if e
* if false then goto jump address if !e
* 2 don't call save87()
* fltarg FLcode or FLblock, flavor of target if e evaluates to jcond
* targ either code or block pointer to destination
*/
void logexp(ref CodeBuilder cdb, elem *e, int jcond, uint fltarg, code *targ)
{
//printf("logexp(e = %p, jcond = %d)\n", e, jcond);
int no87 = (jcond & 2) == 0;
docommas(cdb, &e); // scan down commas
cgstate.stackclean++;
code* c, ce;
if (!OTleaf(e.Eoper) && !e.Ecount) // if operator and not common sub
{
switch (e.Eoper)
{
case OPoror:
{
con_t regconsave;
if (jcond & 1)
{
logexp(cdb, e.EV.E1, jcond, fltarg, targ);
regconsave = regcon;
logexp(cdb, e.EV.E2, jcond, fltarg, targ);
}
else
{
code *cnop = gennop(null);
logexp(cdb, e.EV.E1, jcond | 1, FLcode, cnop);
regconsave = regcon;
logexp(cdb, e.EV.E2, jcond, fltarg, targ);
cdb.append(cnop);
}
andregcon(®consave);
freenode(e);
cgstate.stackclean--;
return;
}
case OPandand:
{
con_t regconsave;
if (jcond & 1)
{
code *cnop = gennop(null); // a dummy target address
logexp(cdb, e.EV.E1, jcond & ~1, FLcode, cnop);
regconsave = regcon;
logexp(cdb, e.EV.E2, jcond, fltarg, targ);
cdb.append(cnop);
}
else
{
logexp(cdb, e.EV.E1, jcond, fltarg, targ);
regconsave = regcon;
logexp(cdb, e.EV.E2, jcond, fltarg, targ);
}
andregcon(®consave);
freenode(e);
cgstate.stackclean--;
return;
}
case OPnot:
jcond ^= 1;
goto case OPbool;
case OPbool:
case OPs8_16:
case OPu8_16:
case OPs16_32:
case OPu16_32:
case OPs32_64:
case OPu32_64:
case OPu32_d:
case OPd_ld:
logexp(cdb, e.EV.E1, jcond, fltarg, targ);
freenode(e);
cgstate.stackclean--;
return;
case OPcond:
{
code *cnop2 = gennop(null); // addresses of start of leaves
code *cnop = gennop(null);
logexp(cdb, e.EV.E1, false, FLcode, cnop2); // eval condition
con_t regconold = regcon;
logexp(cdb, e.EV.E2.EV.E1, jcond, fltarg, targ);
genjmp(cdb, JMP, FLcode, cast(block *) cnop); // skip second leaf
con_t regconsave = regcon;
regcon = regconold;
cdb.append(cnop2);
logexp(cdb, e.EV.E2.EV.E2, jcond, fltarg, targ);
andregcon(®conold);
andregcon(®consave);
freenode(e.EV.E2);
freenode(e);
cdb.append(cnop);
cgstate.stackclean--;
return;
}
default:
break;
}
}
/* Special code for signed long compare.
* Not necessary for I64 until we do cents.
*/
if (OTrel2(e.Eoper) && // if < <= >= >
!e.Ecount &&
( (I16 && tybasic(e.EV.E1.Ety) == TYlong && tybasic(e.EV.E2.Ety) == TYlong) ||
(I32 && tybasic(e.EV.E1.Ety) == TYllong && tybasic(e.EV.E2.Ety) == TYllong))
)
{
longcmp(cdb, e, jcond != 0, fltarg, targ);
cgstate.stackclean--;
return;
}
regm_t retregs = mPSW; // return result in flags
uint op = jmpopcode(e); // get jump opcode
if (!(jcond & 1))
op ^= 0x101; // toggle jump condition(s)
codelem(cdb, e, &retregs, true); // evaluate elem
if (no87)
cse_flush(cdb,no87); // flush CSE's to memory
genjmp(cdb, op, fltarg, cast(block *) targ); // generate jmp instruction
cgstate.stackclean--;
}
/******************************
* Routine to aid in setting things up for gen().
* Look for common subexpression.
* Can handle indirection operators, but not if they're common subs.
* Input:
* e -> elem where we get some of the data from
* cs -> partially filled code to add
* op = opcode
* reg = reg field of (mod reg r/m)
* offset = data to be added to Voffset field
* keepmsk = mask of registers we must not destroy
* desmsk = mask of registers destroyed by executing the instruction
* Returns:
* pointer to code generated
*/
void loadea(ref CodeBuilder cdb,elem *e,code *cs,uint op,uint reg,targ_size_t offset,
regm_t keepmsk,regm_t desmsk)
{
code* c, cg, cd;
debug
if (debugw)
printf("loadea: e=%p cs=%p op=x%x reg=%d offset=%lld keepmsk=%s desmsk=%s\n",
e, cs, op, reg, cast(ulong)offset, regm_str(keepmsk), regm_str(desmsk));
assert(e);
cs.Iflags = 0;
cs.Irex = 0;
cs.Iop = op;
tym_t tym = e.Ety;
int sz = tysize(tym);
/* Determine if location we want to get is in a register. If so, */
/* substitute the register for the EA. */
/* Note that operators don't go through this. CSE'd operators are */
/* picked up by comsub(). */
if (e.Ecount && /* if cse */
e.Ecount != e.Ecomsub && /* and cse was generated */
op != 0x8D && op != 0xC4 && /* and not an LEA or LES */
(op != 0xFF || reg != 3) && /* and not CALLF MEM16 */
(op & 0xFFF8) != 0xD8) // and not 8087 opcode
{
assert(OTleaf(e.Eoper)); /* can't handle this */
regm_t rm = regcon.cse.mval & ~regcon.cse.mops & ~regcon.mvar; // possible regs
if (op == 0xFF && reg == 6)
rm &= ~XMMREGS; // can't PUSH an XMM register
if (sz > REGSIZE) // value is in 2 or 4 registers
{
if (I16 && sz == 8) // value is in 4 registers
{
static immutable regm_t[4] rmask = [ mDX,mCX,mBX,mAX ];
rm &= rmask[cast(size_t)(offset >> 1)];
}
else if (offset)
rm &= mMSW; /* only high words */
else
rm &= mLSW; /* only low words */
}
for (uint i = 0; rm; i++)
{
if (mask(i) & rm)
{
if (regcon.cse.value[i] == e && // if register has elem
/* watch out for a CWD destroying DX */
!(i == DX && op == 0xF7 && desmsk & mDX))
{
/* if ES, then it can only be a load */
if (i == ES)
{
if (op != 0x8B)
break; // not a load
cs.Iop = 0x8C; /* MOV reg,ES */
cs.Irm = modregrm(3, 0, reg & 7);
if (reg & 8)
code_orrex(cs, REX_B);
}
else // XXX reg,i
{
cs.Irm = modregrm(3, reg & 7, i & 7);
if (reg & 8)
cs.Irex |= REX_R;
if (i & 8)
cs.Irex |= REX_B;
if (sz == 1 && I64 && (i >= 4 || reg >= 4))
cs.Irex |= REX;
if (I64 && (sz == 8 || sz == 16))
cs.Irex |= REX_W;
}
goto L2;
}
rm &= ~mask(i);
}
}
}
getlvalue(cdb, cs, e, keepmsk);
if (offset == REGSIZE)
getlvalue_msw(cs);
else
cs.IEV1.Voffset += offset;
if (I64)
{
if (reg >= 4 && sz == 1) // if byte register
// Can only address those 8 bit registers if a REX byte is present
cs.Irex |= REX;
if ((op & 0xFFFFFFF8) == 0xD8)
cs.Irex &= ~REX_W; // not needed for x87 ops
}
code_newreg(cs, reg); // OR in reg field
if (!I16)
{
if (reg == 6 && op == 0xFF || /* don't PUSH a word */
op == 0x0FB7 || op == 0x0FBF || /* MOVZX/MOVSX */
(op & 0xFFF8) == 0xD8 || /* 8087 instructions */
op == 0x8D) /* LEA */
{
cs.Iflags &= ~CFopsize;
if (reg == 6 && op == 0xFF) // if PUSH
cs.Irex &= ~REX_W; // REX is ignored for PUSH anyway
}
}
else if ((op & 0xFFF8) == 0xD8 && ADDFWAIT())
cs.Iflags |= CFwait;
L2:
getregs(cdb, desmsk); // save any regs we destroy
/* KLUDGE! fix up DX for divide instructions */
if (op == 0xF7 && desmsk == (mAX|mDX)) /* if we need to fix DX */
{
if (reg == 7) /* if IDIV */
{
cdb.gen1(0x99); // CWD
if (I64 && sz == 8)
code_orrex(cdb.last(), REX_W);
}
else if (reg == 6) // if DIV
genregs(cdb, 0x33, DX, DX); // XOR DX,DX
}
// Eliminate MOV reg,reg
if ((cs.Iop & ~3) == 0x88 &&
(cs.Irm & 0xC7) == modregrm(3,0,reg & 7))
{
uint r = cs.Irm & 7;
if (cs.Irex & REX_B)
r |= 8;
if (r == reg)
cs.Iop = NOP;
}
cdb.gen(cs);
}
/**************************
* Get addressing mode.
*/
uint getaddrmode(regm_t idxregs)
{
uint mode;
if (I16)
{
static ubyte error() { assert(0); }
mode = (idxregs & mBX) ? modregrm(2,0,7) : /* [BX] */
(idxregs & mDI) ? modregrm(2,0,5): /* [DI] */
(idxregs & mSI) ? modregrm(2,0,4): /* [SI] */
error();
}
else
{
uint reg = findreg(idxregs & (ALLREGS | mBP));
if (reg == R12)
mode = (REX_B << 16) | (modregrm(0,4,4) << 8) | modregrm(2,0,4);
else
mode = modregrmx(2,0,reg);
}
return mode;
}
void setaddrmode(code *c, regm_t idxregs)
{
uint mode = getaddrmode(idxregs);
c.Irm = mode & 0xFF;
c.Isib = (mode >> 8) & 0xFF;
c.Irex &= ~REX_B;
c.Irex |= mode >> 16;
}
/**********************************************
*/
void getlvalue_msw(code *c)
{
if (c.IFL1 == FLreg)
{
uint regmsw = c.IEV1.Vsym.Sregmsw;
c.Irm = (c.Irm & ~7) | (regmsw & 7);
if (regmsw & 8)
c.Irex |= REX_B;
else
c.Irex &= ~REX_B;
}
else
c.IEV1.Voffset += REGSIZE;
}
/**********************************************
*/
void getlvalue_lsw(code *c)
{
if (c.IFL1 == FLreg)
{
uint reglsw = c.IEV1.Vsym.Sreglsw;
c.Irm = (c.Irm & ~7) | (reglsw & 7);
if (reglsw & 8)
c.Irex |= REX_B;
else
c.Irex &= ~REX_B;
}
else
c.IEV1.Voffset -= REGSIZE;
}
/******************
* Compute addressing mode.
* Generate & return sequence of code (if any).
* Return in cs the info on it.
* Input:
* pcs -> where to store data about addressing mode
* e -> the lvalue elem
* keepmsk mask of registers we must not destroy or use
* if (keepmsk & RMstore), this will be only a store operation
* into the lvalue
* if (keepmsk & RMload), this will be a read operation only
*/
void getlvalue(ref CodeBuilder cdb,code *pcs,elem *e,regm_t keepmsk)
{
uint fl, f, opsave;
elem* e1, e11, e12;
bool e1isadd, e1free;
uint reg;
tym_t e1ty;
Symbol* s;
//printf("getlvalue(e = %p, keepmsk = %s)\n", e, regm_str(keepmsk));
//elem_print(e);
assert(e);
elem_debug(e);
if (e.Eoper == OPvar || e.Eoper == OPrelconst)
{
s = e.EV.Vsym;
fl = s.Sfl;
if (tyfloating(s.ty()))
objmod.fltused();
}
else
fl = FLoper;
pcs.IFL1 = cast(ubyte)fl;
pcs.Iflags = CFoff; /* only want offsets */
pcs.Irex = 0;
pcs.IEV1.Voffset = 0;
tym_t ty = e.Ety;
uint sz = tysize(ty);
if (tyfloating(ty))
objmod.fltused();
if (I64 && (sz == 8 || sz == 16) && !tyvector(ty))
pcs.Irex |= REX_W;
if (!I16 && sz == SHORTSIZE)
pcs.Iflags |= CFopsize;
if (ty & mTYvolatile)
pcs.Iflags |= CFvolatile;
switch (fl)
{
case FLoper:
debug
if (debugw) printf("getlvalue(e = %p, keepmsk = %s)\n", e, regm_str(keepmsk));
switch (e.Eoper)
{
case OPadd: // this way when we want to do LEA
e1 = e;
e1free = false;
e1isadd = true;
break;
case OPind:
case OPpostinc: // when doing (*p++ = ...)
case OPpostdec: // when doing (*p-- = ...)
case OPbt:
case OPbtc:
case OPbtr:
case OPbts:
case OPvecfill:
e1 = e.EV.E1;
e1free = true;
e1isadd = e1.Eoper == OPadd;
break;
default:
elem_print(e);
assert(0);
}
e1ty = tybasic(e1.Ety);
if (e1isadd)
{
e12 = e1.EV.E2;
e11 = e1.EV.E1;
}
/* First see if we can replace *(e+&v) with
* MOV idxreg,e
* EA = [ES:] &v+idxreg
*/
f = FLconst;
if (e1isadd &&
((e12.Eoper == OPrelconst
&& (f = el_fl(e12)) != FLfardata
) ||
(e12.Eoper == OPconst && !I16 && !e1.Ecount && (!I64 || el_signx32(e12)))) &&
!(I64 && (config.flags3 & CFG3pic || config.exe == EX_WIN64)) &&
e1.Ecount == e1.Ecomsub &&
(!e1.Ecount || (~keepmsk & ALLREGS & mMSW) || (e1ty != TYfptr && e1ty != TYhptr)) &&
tysize(e11.Ety) == REGSIZE
)
{
uint t; /* component of r/m field */
int ss;
int ssi;
if (e12.Eoper == OPrelconst)
f = el_fl(e12);
/*assert(datafl[f]);*/ /* what if addr of func? */
if (!I16)
{ /* Any register can be an index register */
regm_t idxregs = allregs & ~keepmsk;
assert(idxregs);
/* See if e1.EV.E1 can be a scaled index */
ss = isscaledindex(e11);
if (ss)
{
/* Load index register with result of e11.EV.E1 */
cdisscaledindex(cdb, e11, &idxregs, keepmsk);
reg = findreg(idxregs);
{
t = stackfl[f] ? 2 : 0;
pcs.Irm = modregrm(t, 0, 4);
pcs.Isib = modregrm(ss, reg & 7, 5);
if (reg & 8)
pcs.Irex |= REX_X;
}
}
else if ((e11.Eoper == OPmul || e11.Eoper == OPshl) &&
!e11.Ecount &&
e11.EV.E2.Eoper == OPconst &&
(ssi = ssindex(e11.Eoper, e11.EV.E2.EV.Vuns)) != 0
)
{
regm_t scratchm;
char ssflags = ssindex_array[ssi].ssflags;
if (ssflags & SSFLnobp && stackfl[f])
goto L6;
// Load index register with result of e11.EV.E1
scodelem(cdb, e11.EV.E1, &idxregs, keepmsk, true);
reg = findreg(idxregs);
int ss1 = ssindex_array[ssi].ss1;
if (ssflags & SSFLlea)
{
assert(!stackfl[f]);
pcs.Irm = modregrm(2,0,4);
pcs.Isib = modregrm(ss1, reg & 7, reg & 7);
if (reg & 8)
pcs.Irex |= REX_X | REX_B;
}
else
{
int rbase;
uint r;
scratchm = ALLREGS & ~keepmsk;
allocreg(cdb, &scratchm, &r, TYint);
if (ssflags & SSFLnobase1)
{
t = 0;
rbase = 5;
}
else
{
t = 0;
rbase = reg;
if (rbase == BP || rbase == R13)
{
static immutable uint[4] imm32 = [1+1,2+1,4+1,8+1];
// IMUL r,BP,imm32
cdb.genc2(0x69, modregxrmx(3, r, rbase), imm32[ss1]);
goto L7;
}
}
cdb.gen2sib(0x8D, modregxrm(t, r, 4), modregrm(ss1, reg & 7 ,rbase & 7));
if (reg & 8)
code_orrex(cdb.last(), REX_X);
if (rbase & 8)
code_orrex(cdb.last(), REX_B);
if (I64)
code_orrex(cdb.last(), REX_W);
if (ssflags & SSFLnobase1)
{