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Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111

… )

git-svn-id: http://opencores.org/ocsvn/openmsp430/openmsp430/trunk@128 c36ddccb-d6af-41aa-abd5-588c0c1d0201
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commit c3e71f1514dc86ac214634f5807d6fbc546d706f 1 parent 0902756
olivier.girard authored
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14 core/rtl/verilog/omsp_execution_unit.v
@@ -154,11 +154,9 @@ wire reg_dest_wr = ((e_state==`E_EXEC) & (
inst_type[`INST_JMP])) | dbg_reg_wr;
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
- ((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] &
- ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) |
- inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) |
- ((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
+ ((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
+ ((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
+ ((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
@@ -228,7 +226,7 @@ wire src_reg_src_sel = (e_state==`E_IRQ_0) |
wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
@@ -272,8 +270,8 @@ wire dst_fffe_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) |
- ((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
+ ((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
View
2  core/sim/rtl_sim/bin/template.def
@@ -1,6 +1,6 @@
/* Default linker script, for normal executables */
OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430")
-OUTPUT_ARCH(msp:110)
+OUTPUT_ARCH(msp430)
MEMORY
{
text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE
View
96 core/sim/rtl_sim/src/sing-op_call.s43
@@ -48,6 +48,8 @@
.global main
main:
+ /* -------------- TEST INSTRUCTION WITH STANDARD REGISTERS AS ARGUMENT ------------------- */
+
# Initialization
#------------------------
@@ -139,6 +141,95 @@ main:
mov #0x8000, r15
+ /* -------------- TEST INSTRUCTION WITH SR AS ARGUMENT ------------------- */
+
+
+ # Addressing mode: SR
+ #------------------------
+
+ mov #0x0000, r5
+ nop
+ #call r1 ;# NOT VALID BECAUSE IT JUMPS IN THE DATA MEMORY
+ nop ;# WHICH IS NOT EXECUTABLE
+
+ mov #0x9000, r15
+
+
+ # Addressing mode: @SR
+ #------------------------
+
+ mov #DMEM_252, r1 ;# Initialize stack pointer
+ push #TEST_ROUTINE_RN
+ push #TEST_ROUTINE_aRN
+ push #TEST_ROUTINE_aRNi
+ mov r1, r13 ; backup stack for later
+ push #TEST_ROUTINE_N
+ push #TEST_ROUTINE_xRN
+ push #TEST_ROUTINE_EDE
+ push #TEST_ROUTINE_aEDE
+
+ nop
+ mov r13, r1
+ mov #0x0000, r5
+ nop
+ call @r1 ;# CALL #TEST_ROUTINE_N (r5 = 0xabcd)
+ nop
+
+ mov #0xa000, r15
+
+
+ # Addressing mode: @SR+
+ #------------------------
+
+ mov #DMEM_252, r1 ;# Initialize stack pointer
+ push #TEST_ROUTINE_SPECIAL_aRNi
+ push #TEST_ROUTINE_RN
+ push #TEST_ROUTINE_aRN
+ push #TEST_ROUTINE_aRNi
+ mov r1, r13 ; backup stack for later
+ push #TEST_ROUTINE_N
+ push #TEST_ROUTINE_xRN
+ push #TEST_ROUTINE_EDE
+ push #TEST_ROUTINE_aEDE
+
+ nop
+ mov r13, r1
+ mov #0x0000, r5
+ nop
+ call @r1+ ;# CALL #TEST_ROUTINE_N (this has a funny behavior of nested call backward until SPECIAL_aRNi is reached)
+ nop
+
+ mov #0xb000, r15
+
+
+ # Addressing mode: x(SR)
+ #------------------------
+
+ mov #DMEM_252, r1 ;# Initialize stack pointer
+ push #TEST_ROUTINE_RN
+ push #TEST_ROUTINE_aRN
+ push #TEST_ROUTINE_aRNi
+ push #TEST_ROUTINE_N
+ push #TEST_ROUTINE_xRN
+ push #TEST_ROUTINE_EDE
+ push #TEST_ROUTINE_aEDE
+ nop
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ call 4(r1) ;# CALL #TEST_ROUTINE_EDE (r7 = 0x2345)
+ mov r5, r7
+ mov #0x0000, r5
+ call 6(r1) ;# CALL #TEST_ROUTINE_xRN (r6 = 0xef01)
+ mov r5, r6
+ mov #0x0000, r5
+ call 10(r1) ;# CALL #TEST_ROUTINE_aRNi (r5 = 0x9abc)
+ nop
+
+ mov #0xc000, r15
+
+
+
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
@@ -176,6 +267,11 @@ TEST_ROUTINE_aEDE:
mov #0x6789, r5
ret
+TEST_ROUTINE_SPECIAL_aRNi:
+ mov #0x159a, r5
+ sub #0x000a, r1
+ ret
+
/* ---------------------- INTERRUPT VECTORS --------------- */
View
26 core/sim/rtl_sim/src/sing-op_call.v
@@ -41,6 +41,8 @@ initial
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
+
+ /* -------------- TEST INSTRUCTION WITH STANDARD REGISTERS AS ARGUMENT ------------------- */
// Initialization
@(r15==16'h1000);
@@ -91,6 +93,30 @@ initial
if (r5 !==16'h6789) tb_error("====== CALL (&EDE mode): R5 value =====");
+ /* -------------- TEST INSTRUCTION WITH SR AS ARGUMENT ------------------- */
+
+
+ // Addressing mode: SR
+ @(r15==16'h9000);
+ // --> not tested because it would require the cpu to execute from the data memory
+
+
+ // Addressing mode: @SR
+ @(r15==16'hA000);
+ if (r5 !==16'habcd) tb_error("====== CALL @SR : R5 value =====");
+
+
+ // Addressing mode: @SR+
+ @(r15==16'hB000);
+ if (r5 !==16'h159a) tb_error("====== CALL @SR+ : R5 value =====");
+
+
+ // Addressing mode: x(SR)
+ @(r15==16'hC000);
+ if (r5 !==16'h9abc) tb_error("====== CALL x(SR) : R5 value =====");
+ if (r6 !==16'hef01) tb_error("====== CALL x(SR) : R6 value =====");
+ if (r7 !==16'h2345) tb_error("====== CALL x(SR) : R7 value =====");
+
stimulus_done = 1;
end
View
59 fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
@@ -1,24 +1,29 @@
//----------------------------------------------------------------------------
-// Copyright (C) 2001 Authors
+// Copyright (C) 2009 , Olivier Girard
//
-// This source file may be used and distributed without restriction provided
-// that this copyright statement is not removed from the file and that any
-// derivative work contains the original copyright notice and the associated
-// disclaimer.
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// * Neither the name of the authors nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
//
-// This source file is free software; you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published
-// by the Free Software Foundation; either version 2.1 of the License, or
-// (at your option) any later version.
-//
-// This source is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
-// License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this source; if not, write to the Free Software Foundation,
-// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
@@ -31,9 +36,9 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
-// $Rev: 103 $
+// $Rev: 117 $
// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
+// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
@@ -149,11 +154,9 @@ wire reg_dest_wr = ((e_state==`E_EXEC) & (
inst_type[`INST_JMP])) | dbg_reg_wr;
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
- ((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] &
- ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) |
- inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) |
- ((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
+ ((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
+ ((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
+ ((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
@@ -223,7 +226,7 @@ wire src_reg_src_sel = (e_state==`E_IRQ_0) |
wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
@@ -267,8 +270,8 @@ wire dst_fffe_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) |
- ((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
+ ((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
View
55 fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v
@@ -1,24 +1,29 @@
//----------------------------------------------------------------------------
-// Copyright (C) 2001 Authors
+// Copyright (C) 2009 , Olivier Girard
//
-// This source file may be used and distributed without restriction provided
-// that this copyright statement is not removed from the file and that any
-// derivative work contains the original copyright notice and the associated
-// disclaimer.
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// * Neither the name of the authors nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
//
-// This source file is free software; you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published
-// by the Free Software Foundation; either version 2.1 of the License, or
-// (at your option) any later version.
-//
-// This source is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
-// License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this source; if not, write to the Free Software Foundation,
-// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
@@ -149,11 +154,9 @@ wire reg_dest_wr = ((e_state==`E_EXEC) & (
inst_type[`INST_JMP])) | dbg_reg_wr;
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
- ((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] &
- ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) |
- inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) |
- ((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
+ ((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
+ ((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
+ ((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
@@ -223,7 +226,7 @@ wire src_reg_src_sel = (e_state==`E_IRQ_0) |
wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
@@ -267,8 +270,8 @@ wire dst_fffe_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) |
- ((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
+ ((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
View
55 fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v
@@ -1,24 +1,29 @@
//----------------------------------------------------------------------------
-// Copyright (C) 2001 Authors
+// Copyright (C) 2009 , Olivier Girard
//
-// This source file may be used and distributed without restriction provided
-// that this copyright statement is not removed from the file and that any
-// derivative work contains the original copyright notice and the associated
-// disclaimer.
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// * Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// * Neither the name of the authors nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
//
-// This source file is free software; you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published
-// by the Free Software Foundation; either version 2.1 of the License, or
-// (at your option) any later version.
-//
-// This source is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
-// License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this source; if not, write to the Free Software Foundation,
-// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
@@ -149,11 +154,9 @@ wire reg_dest_wr = ((e_state==`E_EXEC) & (
inst_type[`INST_JMP])) | dbg_reg_wr;
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
- ((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] &
- ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) |
- inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) |
- ((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
+ ((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
+ ((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
+ ((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
@@ -223,7 +226,7 @@ wire src_reg_src_sel = (e_state==`E_IRQ_0) |
wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
@@ -267,8 +270,8 @@ wire dst_fffe_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
- ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) |
- ((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
+ ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
+ ((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |

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