"Scratch DDR SDRAM Controller" from OpenCores (with newlines fixed using "git filter-branch")
VHDL Verilog
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boards
LGPLv3.txt
ddr.v
ddr_parameters.vh
scratch.vhd
scratch_isim_tb.vhd
sdram.vhd
sdram_init.vhd
sdram_reader.vhd
sdram_support.vhd
sdram_writer.vhd