New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[LLVM CodeGen] Solve LLVM CodeGen br instruction accept not-i1 type issue #2381

Merged
merged 2 commits into from Jan 8, 2019

Conversation

Projects
None yet
2 participants
@FrozenGene
Copy link
Contributor

FrozenGene commented Jan 7, 2019

see issue: #2364

LLVM br instruction can only accept i1 type of condition (https://llvm.org/docs/LangRef.html#br-instruction), if the condition type is not i1, we couldn't rewrite to tvm_if_then_else, which is converted to LLVM br instruction. This situation could happen in the situation conv2d + prelu via auto tvm tunning on ARM CPU.

@tqchen please help to review it.
cc: @nttstar

@tqchen

This comment has been minimized.

Copy link
Member

tqchen commented Jan 7, 2019

This is a bit strange, shall we make sure the condition of prelu is bool instead?

@FrozenGene

This comment has been minimized.

Copy link
Contributor

FrozenGene commented Jan 7, 2019

Prelu is implemented in select statement, prelu helps us expose this issue. In theory, we can constrtuct other cases using select (condition type is N x i1) to expose this issue.

@FrozenGene

This comment has been minimized.

Copy link
Contributor

FrozenGene commented Jan 8, 2019

Supplement of previous comment. LLVM select instruction can accept i1 or vector of i1 (N xi1) type, see: https://llvm.org/docs/LangRef.html#select-instruction But br can only accept i1 type, so this is why I say we can construct using select (N x i1) to expose this issue.

@tqchen

tqchen approved these changes Jan 8, 2019

@tqchen tqchen merged commit 536ba30 into dmlc:master Jan 8, 2019

1 check passed

continuous-integration/jenkins/pr-merge This commit looks good
Details
@tqchen

This comment has been minimized.

Copy link
Member

tqchen commented Jan 8, 2019

Thanks, @FrozenGene for the explaination. I have a follow-up PR that is related #2389 The root cause of this error is when if_then_else get vectorized which causes incorrect semantics.

FrozenGene added a commit to FrozenGene/tvm that referenced this pull request Jan 10, 2019

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment