Merge pull request #10010 from AdmiralCurtiss/jit-cache-translate-add…

…ress-cleanup

PowerPC: Minor cleanup around JitCache_TranslateAddress().

Source/Core/Core/PowerPC/JitCommon/JitCache.cpp

@@ -96,10 +96,10 @@ void JitBaseBlockCache::RunOnBlocks(std::function<void(const JitBlock&)> f)
 
 JitBlock* JitBaseBlockCache::AllocateBlock(u32 em_address)
 {
-  u32 physicalAddress = PowerPC::JitCache_TranslateAddress(em_address).address;
-  JitBlock& b = block_map.emplace(physicalAddress, JitBlock())->second;
+  const u32 physical_address = PowerPC::JitCache_TranslateAddress(em_address).address;
+  JitBlock& b = block_map.emplace(physical_address, JitBlock())->second;
   b.effectiveAddress = em_address;
-  b.physicalAddress = physicalAddress;
+  b.physicalAddress = physical_address;
   b.msrBits = MSR.Hex & JIT_CACHE_MSR_MASK;
   b.linkData.clear();
   b.fast_block_map_index = 0;
@@ -185,25 +185,25 @@ const u8* JitBaseBlockCache::Dispatch()
 
 void JitBaseBlockCache::InvalidateICache(u32 address, u32 length, bool forced)
 {
-  auto translated = PowerPC::JitCache_TranslateAddress(address);
+  const auto translated = PowerPC::JitCache_TranslateAddress(address);
   if (!translated.valid)
     return;
-  u32 pAddr = translated.address;
+  const u32 physical_address = translated.address;
 
   // Optimize the common case of length == 32 which is used by Interpreter::dcb*
   bool destroy_block = true;
   if (length == 32)
   {
-    if (!valid_block.Test(pAddr / 32))
+    if (!valid_block.Test(physical_address / 32))
       destroy_block = false;
     else
-      valid_block.Clear(pAddr / 32);
+      valid_block.Clear(physical_address / 32);
   }
 
   if (destroy_block)
   {
     // destroy JIT blocks
-    ErasePhysicalRange(pAddr, length);
+    ErasePhysicalRange(physical_address, length);
 
     // If the code was actually modified, we need to clear the relevant entries from the
     // FIFO write address cache, so we don't end up with FIFO checks in places they shouldn't

Source/Core/Core/PowerPC/MMU.cpp

@@ -99,18 +99,25 @@ static bool IsNoExceptionFlag(XCheckTLBFlag flag)
   return flag == XCheckTLBFlag::NoException || flag == XCheckTLBFlag::OpcodeNoException;
 }
 
+enum class TranslateAddressResultEnum : u8
+{
+  BAT_TRANSLATED,
+  PAGE_TABLE_TRANSLATED,
+  DIRECT_STORE_SEGMENT,
+  PAGE_FAULT,
+};
+
 struct TranslateAddressResult
 {
-  enum
-  {
-    BAT_TRANSLATED,
-    PAGE_TABLE_TRANSLATED,
-    DIRECT_STORE_SEGMENT,
-    PAGE_FAULT
-  } result;
   u32 address;
+  TranslateAddressResultEnum result;
   bool wi;  // Set to true if the view of memory is either write-through or cache-inhibited
-  bool Success() const { return result <= PAGE_TABLE_TRANSLATED; }
+
+  TranslateAddressResult(TranslateAddressResultEnum result_, u32 address_, bool wi_ = false)
+      : address(address_), result(result_), wi(wi_)
+  {
+  }
+  bool Success() const { return result <= TranslateAddressResultEnum::PAGE_TABLE_TRANSLATED; }
 };
 template <const XCheckTLBFlag flag>
 static TranslateAddressResult TranslateAddress(u32 address);
@@ -444,7 +451,7 @@ TryReadInstResult TryReadInstruction(u32 address)
     else
     {
       address = tlb_addr.address;
-      from_bat = tlb_addr.result == TranslateAddressResult::BAT_TRANSLATED;
+      from_bat = tlb_addr.result == TranslateAddressResultEnum::BAT_TRANSLATED;
     }
   }
 
@@ -1023,14 +1030,14 @@ void ClearCacheLine(u32 address)
   if (MSR.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
-    if (translated_address.result == TranslateAddressResult::DIRECT_STORE_SEGMENT)
+    if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
     {
       // dcbz to direct store segments is ignored. This is a little
       // unintuitive, but this is consistent with both console and the PEM.
       // Advance Game Port crashes if we don't emulate this correctly.
       return;
     }
-    if (translated_address.result == TranslateAddressResult::PAGE_FAULT)
+    if (translated_address.result == TranslateAddressResultEnum::PAGE_FAULT)
     {
       // If translation fails, generate a DSI.
       GenerateDSIException(address, true);
@@ -1090,17 +1097,15 @@ bool IsOptimizableGatherPipeWrite(u32 address)
 TranslateResult JitCache_TranslateAddress(u32 address)
 {
   if (!MSR.IR)
-    return TranslateResult{true, true, address};
+    return TranslateResult{address};
 
   // TODO: We shouldn't use FLAG_OPCODE if the caller is the debugger.
-  auto tlb_addr = TranslateAddress<XCheckTLBFlag::Opcode>(address);
+  const auto tlb_addr = TranslateAddress<XCheckTLBFlag::Opcode>(address);
   if (!tlb_addr.Success())
-  {
-    return TranslateResult{false, false, 0};
-  }
+    return TranslateResult{};
 
-  bool from_bat = tlb_addr.result == TranslateAddressResult::BAT_TRANSLATED;
-  return TranslateResult{true, from_bat, tlb_addr.address};
+  const bool from_bat = tlb_addr.result == TranslateAddressResultEnum::BAT_TRANSLATED;
+  return TranslateResult{from_bat, tlb_addr.address};
 }
 
 // *********************************************************************************
@@ -1343,20 +1348,21 @@ static TranslateAddressResult TranslatePageAddress(const u32 address, const XChe
   u32 translatedAddress = 0;
   TLBLookupResult res = LookupTLBPageAddress(flag, address, &translatedAddress, wi);
   if (res == TLBLookupResult::Found)
-    return TranslateAddressResult{TranslateAddressResult::PAGE_TABLE_TRANSLATED, translatedAddress};
+    return TranslateAddressResult{TranslateAddressResultEnum::PAGE_TABLE_TRANSLATED,
+                                  translatedAddress};
 
   u32 sr = PowerPC::ppcState.sr[EA_SR(address)];
 
   if (sr & 0x80000000)
-    return TranslateAddressResult{TranslateAddressResult::DIRECT_STORE_SEGMENT, 0};
+    return TranslateAddressResult{TranslateAddressResultEnum::DIRECT_STORE_SEGMENT, 0};
 
   // TODO: Handle KS/KP segment register flags.
 
   // No-execute segment register flag.
   if ((flag == XCheckTLBFlag::Opcode || flag == XCheckTLBFlag::OpcodeNoException) &&
       (sr & 0x10000000))
   {
-    return TranslateAddressResult{TranslateAddressResult::PAGE_FAULT, 0};
+    return TranslateAddressResult{TranslateAddressResultEnum::PAGE_FAULT, 0};
   }
 
   u32 offset = EA_Offset(address);         // 12 bit
@@ -1418,12 +1424,12 @@ static TranslateAddressResult TranslatePageAddress(const u32 address, const XChe
 
         *wi = (PTE2.WIMG & 0b1100) != 0;
 
-        return TranslateAddressResult{TranslateAddressResult::PAGE_TABLE_TRANSLATED,
+        return TranslateAddressResult{TranslateAddressResultEnum::PAGE_TABLE_TRANSLATED,
                                       (PTE2.RPN << 12) | offset};
       }
     }
   }
-  return TranslateAddressResult{TranslateAddressResult::PAGE_FAULT, 0};
+  return TranslateAddressResult{TranslateAddressResultEnum::PAGE_FAULT, 0};
 }
 
 static void UpdateBATs(BatTable& bat_table, u32 base_spr)
@@ -1583,7 +1589,7 @@ static TranslateAddressResult TranslateAddress(u32 address)
   bool wi = false;
 
   if (TranslateBatAddess(IsOpcodeFlag(flag) ? ibat_table : dbat_table, &address, &wi))
-    return TranslateAddressResult{TranslateAddressResult::BAT_TRANSLATED, address, wi};
+    return TranslateAddressResult{TranslateAddressResultEnum::BAT_TRANSLATED, address, wi};
 
   return TranslatePageAddress(address, flag, &wi);
 }

Source/Core/Core/PowerPC/MMU.h

@@ -189,9 +189,17 @@ bool IsOptimizableGatherPipeWrite(u32 address);
 
 struct TranslateResult
 {
-  bool valid;
-  bool from_bat;
-  u32 address;
+  bool valid = false;
+  bool translated = false;
+  bool from_bat = false;
+  u32 address = 0;
+
+  TranslateResult() = default;
+  explicit TranslateResult(u32 address_) : valid(true), address(address_) {}
+  TranslateResult(bool from_bat_, u32 address_)
+      : valid(true), translated(true), from_bat(from_bat_), address(address_)
+  {
+  }
 };
 TranslateResult JitCache_TranslateAddress(u32 address);