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[ARM] Flush the fpr cache between every instruction. Do this until I …
…figure out what is destroying the FPR register states.
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Sonicadvance1 committed Sep 16, 2013
1 parent 7397867 commit 1529bb4
Showing 1 changed file with 1 addition and 0 deletions.
1 change: 1 addition & 0 deletions Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
Expand Up @@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
BKPT(0x7777);
}
JitArmTables::CompileInstruction(ops[i]);
fpr.Flush();
if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
{
// Don't do this yet
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