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Merge pull request #842 from lioncash/jit
Coding style clean up for the Jit, JitARM and JitIL
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lioncash committed Aug 21, 2014
2 parents f17dcd2 + 20f8ec9 commit 25e29c3
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Showing 42 changed files with 2,413 additions and 1,046 deletions.
8 changes: 6 additions & 2 deletions Source/Core/Core/PowerPC/Jit64/Jit.cpp
Expand Up @@ -162,7 +162,9 @@ void Jit64::Init()
jo.enableBlocklink = false;
}
else
{
jo.enableBlocklink = !Core::g_CoreStartupParameter.bMMU;
}
}
jo.fpAccurateFcmp = Core::g_CoreStartupParameter.bEnableFPRF;
jo.optimizeGatherPipe = true;
Expand Down Expand Up @@ -435,7 +437,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
ABI_CallFunction((void *)&ImHere); //Used to get a trace of the last few blocks before a crash, sometimes VERY useful

// Conditionally add profiling code.
if (Profiler::g_ProfileBlocks) {
if (Profiler::g_ProfileBlocks)
{
ADD(32, M(&b->runCount), Imm8(1));
#ifdef _WIN32
b->ticCounter = 0;
Expand Down Expand Up @@ -617,7 +620,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
//NOTICE_LOG(DYNA_REC, "Unflushed register: %s", ppc_inst.c_str());
}
#endif
if (js.skipnext) {
if (js.skipnext)
{
js.skipnext = false;
i++; // Skip next instruction
}
Expand Down
12 changes: 8 additions & 4 deletions Source/Core/Core/PowerPC/Jit64/Jit.h
Expand Up @@ -68,18 +68,22 @@ class Jit64 : public Jitx86Base

void ClearCache() override;

const u8 *GetDispatcher() {
const u8 *GetDispatcher()
{
return asm_routines.dispatcher;
}
const CommonAsmRoutines *GetAsmRoutines() override {

const CommonAsmRoutines *GetAsmRoutines() override
{
return &asm_routines;
}

const char *GetName() override {
const char *GetName() override
{
return "JIT64";
}
// Run!

// Run!
void Run() override;
void SingleStep() override;

Expand Down
6 changes: 4 additions & 2 deletions Source/Core/Core/PowerPC/Jit64/JitAsm.h
Expand Up @@ -27,13 +27,15 @@ class Jit64AsmRoutineManager : public CommonAsmRoutines
void GenerateCommon();

public:
void Init() {
void Init()
{
AllocCodeSpace(8192);
Generate();
WriteProtect();
}

void Shutdown() {
void Shutdown()
{
FreeCodeSpace();
}
};
29 changes: 22 additions & 7 deletions Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
Expand Up @@ -52,21 +52,35 @@ void RegCache::Start()
void RegCache::Lock(int p1, int p2, int p3, int p4)
{
regs[p1].locked = true;
if (p2 != 0xFF) regs[p2].locked = true;
if (p3 != 0xFF) regs[p3].locked = true;
if (p4 != 0xFF) regs[p4].locked = true;

if (p2 != 0xFF)
regs[p2].locked = true;

if (p3 != 0xFF)
regs[p3].locked = true;

if (p4 != 0xFF)
regs[p4].locked = true;
}

// these are x64 reg indices
void RegCache::LockX(int x1, int x2, int x3, int x4)
{
if (xregs[x1].locked) {
if (xregs[x1].locked)
{
PanicAlert("RegCache: x %i already locked!", x1);
}

xregs[x1].locked = true;
if (x2 != 0xFF) xregs[x2].locked = true;
if (x3 != 0xFF) xregs[x3].locked = true;
if (x4 != 0xFF) xregs[x4].locked = true;

if (x2 != 0xFF)
xregs[x2].locked = true;

if (x3 != 0xFF)
xregs[x3].locked = true;

if (x4 != 0xFF)
xregs[x4].locked = true;
}

void RegCache::UnlockAll()
Expand Down Expand Up @@ -321,6 +335,7 @@ void RegCache::Flush(FlushMode mode)
{
PanicAlert("Someone forgot to unlock PPC reg %" PRIx64 " (X64 reg %i).", i, RX(i));
}

if (regs[i].away)
{
if (regs[i].location.IsSimpleReg() || regs[i].location.IsImm())
Expand Down
27 changes: 21 additions & 6 deletions Source/Core/Core/PowerPC/Jit64/JitRegCache.h
Expand Up @@ -47,23 +47,34 @@ class RegCache

public:
RegCache();

virtual ~RegCache() {}

void Start();

void DiscardRegContentsIfCached(size_t preg);
void SetEmitter(Gen::XEmitter *emitter) {emit = emitter;}
void SetEmitter(Gen::XEmitter *emitter)
{
emit = emitter;
}

void FlushR(Gen::X64Reg reg);
void FlushR(Gen::X64Reg reg, Gen::X64Reg reg2) {FlushR(reg); FlushR(reg2);}
void FlushLockX(Gen::X64Reg reg) {
void FlushR(Gen::X64Reg reg, Gen::X64Reg reg2)
{
FlushR(reg);
FlushR(reg2);
}

void FlushLockX(Gen::X64Reg reg)
{
FlushR(reg);
LockX(reg);
}
void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2) {
void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2)
{
FlushR(reg1); FlushR(reg2);
LockX(reg1); LockX(reg2);
}

void Flush(FlushMode mode = FLUSH_ALL);
void Flush(PPCAnalyst::CodeOp *op) {Flush();}
int SanityCheck() const;
Expand All @@ -76,7 +87,11 @@ class RegCache
virtual void StoreRegister(size_t preg, Gen::OpArg newLoc) = 0;
virtual void LoadRegister(size_t preg, Gen::X64Reg newLoc) = 0;

const Gen::OpArg &R(size_t preg) const {return regs[preg].location;}
const Gen::OpArg &R(size_t preg) const
{
return regs[preg].location;
}

Gen::X64Reg RX(size_t preg) const
{
if (IsBound(preg))
Expand Down
3 changes: 2 additions & 1 deletion Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp
Expand Up @@ -67,7 +67,8 @@ void Jit64::bx(UGeckoInstruction inst)
// If this is not the last instruction of a block,
// we will skip the rest process.
// Because PPCAnalyst::Flatten() merged the blocks.
if (!js.isLastInstruction) {
if (!js.isLastInstruction)
{
return;
}

Expand Down
10 changes: 7 additions & 3 deletions Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp
Expand Up @@ -136,10 +136,13 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
fpr.BindToRegister(d, false);
//YES it is necessary to dupe the result :(
//TODO : analysis - does the top reg get used? If so, dupe, if not, don't.
if (single_precision) {
if (single_precision)
{
ForceSinglePrecisionS(XMM0);
MOVDDUP(fpr.RX(d), R(XMM0));
} else {
}
else
{
MOVSD(fpr.RX(d), R(XMM0));
}
// SMB checks flags after this op. Let's lie.
Expand All @@ -159,7 +162,8 @@ void Jit64::fsign(UGeckoInstruction inst)
fpr.Lock(b, d);
fpr.BindToRegister(d, true, true);
MOVSD(XMM0, fpr.R(b));
switch (inst.SUBOP10) {
switch (inst.SUBOP10)
{
case 40: // fnegx
PXOR(XMM0, M((void*)&psSignBits2));
break;
Expand Down

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