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Interpreter_Integer: Correct negative overflow handling for divw
Previously, given cases such as 0x80000000 / 0xFFFFFFFF we'd incorrectly set the destination register value to zero. If the dividend is negative, then the destination should be set to -1 (0xFFFFFFFF), however if the dividend is positive, then the destination should be set to 0. Note that the 750CL documents state that: "If an attempt is made to perform either of the divisions -- 0x80000000 / -1 or <anything> / 0, then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set." So this is a particular behavior of the hardware itself.
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