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[ARM] Merge load instructions in to one. Also rapid prototype 13 more…
… load instructions. This disables fastmem currently for loads.
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Sonicadvance1 committed Sep 3, 2013
1 parent d4d6eb5 commit 30cd436
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Showing 3 changed files with 174 additions and 260 deletions.
8 changes: 3 additions & 5 deletions Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
Expand Up @@ -126,6 +126,8 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
// TODO: This shouldn't be here
void UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset);
void SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset);

void SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse);
void LoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offset);


Expand Down Expand Up @@ -176,14 +178,10 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock

// LoadStore
void stX(UGeckoInstruction _inst);
void lXX(UGeckoInstruction _inst);

void icbi(UGeckoInstruction _inst);
void dcbst(UGeckoInstruction _inst);
void lbz(UGeckoInstruction _inst);
void lhz(UGeckoInstruction _inst);
void lha(UGeckoInstruction _inst);
void lwz(UGeckoInstruction _inst);
void lwzx(UGeckoInstruction _inst);

// Floating point
void fabsx(UGeckoInstruction _inst);
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