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Interpreter_FPUtils: Correct setting the FPSCR's zero divide exceptio…
…n flag in the 0/0 case FPSCR[ZX] is the bit defined to represent the zero divide exception condition bit, and is defined as (according to PowerPC Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors, which will be referred to as "PEM" for the rest of this commit message) at section 188.8.131.52: " A zero divide exception condition occurs when a divide instructions is executed with a zero divisor value and a finite, nonzero dividend value or when a floating reciprocal estimate single (fres) or a floating reciprocal square root estimate (frsqrte) instruction is executed with a zero operand value. " Note that it states the divisor must be zero and the dividend must be nonzero in order for ZX to be set. This means that the interpreter was performing the wrong behavior for the case where 0/0 (with any sign on the zeros) is performed. We would incorrectly set the ZX bit when only the VXZDZ bit should be set. It's also worth pointing out that N/0 (where N is any finite nonzero value) and 0/0 are not within the same exception class. N/0 is a zero divide exception case, while 0/0 is considered an invalid operation exception case, which is also indicated in the PEM section 184.108.40.206 as well where it lists the criteria for invalid operation exceptions. Therefore we should only be setting the VXZDZ bit in the 0/0 case, not VXZDZ and ZX. This was also verified via hardware tests to ensure that this behavior indeed holds.
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