Skip to content

Commit

Permalink
Browse files Browse the repository at this point in the history
Merge pull request #11181 from JosJuice/jitarm64-25-bit-urshr 
JitArm64: Reimplement Force25BitPrecision
  • Loading branch information
@degasus
degasus committed Oct 22, 2022
2 parents 5c7b551 + 4dbf0b8 commit 583c2b8
Show file tree
Hide file tree
Showing 5 changed files with 57 additions and 32 deletions.
37 changes: 35 additions & 2 deletions Source/Core/Common/Arm64Emitter.cpp
View file
Expand Up @@ -2354,7 +2354,7 @@ void ARM64FloatEmitter::EmitShiftImm(bool Q, bool U, u32 imm, u32 opcode, ARM64R

void ARM64FloatEmitter::EmitScalarShiftImm(bool U, u32 imm, u32 opcode, ARM64Reg Rd, ARM64Reg Rn)
{
Write32((2 << 30) | (U << 29) | (0x3E << 23) | (imm << 16) | (opcode << 11) | (1 << 10) |
Write32((1 << 30) | (U << 29) | (0x3E << 23) | (imm << 16) | (opcode << 11) | (1 << 10) |
(DecodeReg(Rn) << 5) | DecodeReg(Rd));
}

Expand Down Expand Up @@ -3540,7 +3540,26 @@ void ARM64FloatEmitter::ZIP2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
EmitPermute(size, 0b111, Rd, Rn, Rm);
}

// Shift by immediate
// Scalar shift by immediate
void ARM64FloatEmitter::SHL(ARM64Reg Rd, ARM64Reg Rn, u32 shift)
{
constexpr size_t src_size = 64;
ASSERT_MSG(DYNA_REC, IsDouble(Rd), "Only double registers are supported!");
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}",
shift, src_size);
EmitScalarShiftImm(0, src_size | shift, 0b01010, Rd, Rn);
}

void ARM64FloatEmitter::URSHR(ARM64Reg Rd, ARM64Reg Rn, u32 shift)
{
constexpr size_t src_size = 64;
ASSERT_MSG(DYNA_REC, IsDouble(Rd), "Only double registers are supported!");
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}",
shift, src_size);
EmitScalarShiftImm(1, src_size * 2 - shift, 0b00100, Rd, Rn);
}

// Vector shift by immediate
void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift)
{
SSHLL(src_size, Rd, Rn, shift, false);
Expand Down Expand Up @@ -3582,13 +3601,27 @@ void ARM64FloatEmitter::UXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn)
UXTL(src_size, Rd, Rn, true);
}

void ARM64FloatEmitter::SHL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift)
{
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}",
shift, src_size);
EmitShiftImm(1, 0, src_size | shift, 0b01010, Rd, Rn);
}

void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper)
{
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}",
shift, src_size);
EmitShiftImm(upper, 0, src_size | shift, 0b10100, Rd, Rn);
}

void ARM64FloatEmitter::URSHR(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift)
{
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must less than the element size! {} {}",
shift, src_size);
EmitShiftImm(1, 1, src_size * 2 - shift, 0b00100, Rd, Rn);
}

void ARM64FloatEmitter::USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper)
{
ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}",
Expand Down
8 changes: 7 additions & 1 deletion Source/Core/Common/Arm64Emitter.h
View file
Expand Up @@ -1229,9 +1229,15 @@ class ARM64FloatEmitter
void TRN2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void ZIP2(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);

// Shift by immediate
// Scalar shift by immediate
void SHL(ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void URSHR(ARM64Reg Rd, ARM64Reg Rn, u32 shift);

// Vector shift by immediate
void SHL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void SSHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void URSHR(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void USHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
void SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
Expand Down
3 changes: 1 addition & 2 deletions Source/Core/Core/PowerPC/JitArm64/Jit.h
View file
Expand Up @@ -333,8 +333,7 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock, public CommonA
bool Rc = false);

void SetFPRFIfNeeded(bool single, Arm64Gen::ARM64Reg reg);
void Force25BitPrecision(Arm64Gen::ARM64Reg output, Arm64Gen::ARM64Reg input,
Arm64Gen::ARM64Reg temp);
void Force25BitPrecision(Arm64Gen::ARM64Reg output, Arm64Gen::ARM64Reg input);

// <Fastmem fault location, slowmem handler location>
std::map<const u8*, FastmemArea> m_fault_to_handler;
Expand Down
33 changes: 12 additions & 21 deletions Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
View file
Expand Up @@ -45,24 +45,18 @@ void JitArm64::SetFPRFIfNeeded(bool single, ARM64Reg reg)
// Emulate the odd truncation/rounding that the PowerPC does on the RHS operand before
// a single precision multiply. To be precise, it drops the low 28 bits of the mantissa,
// rounding to nearest as it does.
void JitArm64::Force25BitPrecision(ARM64Reg output, ARM64Reg input, ARM64Reg temp)
void JitArm64::Force25BitPrecision(ARM64Reg output, ARM64Reg input)
{
ASSERT(output != input && output != temp && input != temp);

// temp = 0x0000'0000'0800'0000ULL
// output = 0xFFFF'FFFF'F800'0000ULL
m_float_emit.MOVI(32, temp, 0x08, 24);
m_float_emit.MOVI(64, output, 0xFFFF'FFFF'0000'0000ULL);
m_float_emit.BIC(temp, temp, output);
m_float_emit.ORR(32, output, 0xF8, 24);

// output = (input & ~0xFFFFFFF) + ((input & (1ULL << 27)) << 1)
m_float_emit.AND(temp, input, temp);
m_float_emit.AND(output, input, output);
if (IsQuad(input))
m_float_emit.ADD(64, output, output, temp);
{
m_float_emit.URSHR(64, output, input, 28);
m_float_emit.SHL(64, output, output, 28);
}
else
m_float_emit.ADD(output, output, temp);
{
m_float_emit.URSHR(output, input, 28);
m_float_emit.SHL(output, output, 28);
}
}

void JitArm64::fp_arith(UGeckoInstruction inst)
Expand Down Expand Up @@ -113,9 +107,8 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");

V0Q = fpr.GetReg();
V1Q = fpr.GetReg();

Force25BitPrecision(reg_encoder(V0Q), VC, reg_encoder(V1Q));
Force25BitPrecision(reg_encoder(V0Q), VC);
VC = reg_encoder(V0Q);
}

Expand Down Expand Up @@ -160,18 +153,16 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
{
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");

V0Q = fpr.GetReg();
V1Q = fpr.GetReg();

Force25BitPrecision(reg_encoder(V1Q), VC, reg_encoder(V0Q));
Force25BitPrecision(reg_encoder(V1Q), VC);
VC = reg_encoder(V1Q);
}

ARM64Reg inaccurate_fma_temp_reg = VD;
if (inaccurate_fma && d == b)
{
if (V0Q == ARM64Reg::INVALID_REG)
V0Q = fpr.GetReg();
V0Q = fpr.GetReg();

inaccurate_fma_temp_reg = reg_encoder(V0Q);
}
Expand Down
8 changes: 2 additions & 6 deletions Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
View file
Expand Up @@ -103,12 +103,9 @@ void JitArm64::ps_mulsX(UGeckoInstruction inst)
ASSERT_MSG(DYNA_REC, !singles, "Tried to apply 25-bit precision to single");

V0Q = fpr.GetReg();
const ARM64Reg V1Q = fpr.GetReg();

Force25BitPrecision(reg_encoder(V0Q), reg_encoder(VC), reg_encoder(V1Q));
Force25BitPrecision(reg_encoder(V0Q), reg_encoder(VC));
VC = reg_encoder(V0Q);

fpr.Unlock(V1Q);
}

m_float_emit.FMUL(size, reg_encoder(VD), reg_encoder(VA), reg_encoder(VC), upper ? 1 : 0);
Expand Down Expand Up @@ -165,10 +162,9 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
{
ASSERT_MSG(DYNA_REC, !singles, "Tried to apply 25-bit precision to single");

allocate_v0_if_needed();
V1Q = fpr.GetReg();

Force25BitPrecision(reg_encoder(V1Q), VC, V0);
Force25BitPrecision(reg_encoder(V1Q), VC);
VC = reg_encoder(V1Q);
}

Expand Down

0 comments on commit 583c2b8

Please sign in to comment.