Fix fastmem on ARM

dolphin-emu · Apr 12, 2013 · 62adcaf · 62adcaf
1 parent 6d9c0c8
commit 62adcaf
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Showing 3 changed files with 7 additions and 6 deletions.
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp
@@ -33,6 +33,7 @@ using namespace ArmGen;
 	{
 		ARMXEmitter emit(location);
 		emit.B(address);
+		emit.FlushIcache();
 	}
 	void JitArmBlockCache::WriteDestroyBlock(const u8* location, u32 address)
 	{
@@ -41,6 +42,7 @@ using namespace ArmGen;
 		emit.MOVI2R(R12, (u32)jit->GetAsmRoutines()->dispatcher);
 		emit.STR(R11, R9, PPCSTATE_OFF(pc));
 		emit.B(R12);
+		emit.FlushIcache();
 	}
 
 
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
@@ -50,33 +50,32 @@ static void BackPatchError(const std::string &text, u8 *codePtr, u32 emAddress)
 bool DisamLoadStore(const u32 inst, ARMReg &rD, u8 &accessSize, bool &Store)
 {
 	u8 op = (inst >> 20) & 0xFF;
-	printf("op: 0x%08x\n", op);
 	switch (op)
 	{
 		case 0x58: // STR
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = true;
 			accessSize = 32;
 		}
 		break;
 		case 0x59: // LDR
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize = 32;
 		}
 		break;
 		case 0x05: // LDRH
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize = 16;
 		}
 		break;
 		case 0x45 + 0x18: // LDRB
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize  = 8;
 		}

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
@@ -34,7 +34,7 @@
 #ifdef ANDROID
 #define FASTMEM 0
 #else
-#define FASTMEM 0
+#define FASTMEM 1
 #endif
 void JitArm::stw(UGeckoInstruction inst)
 {