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Merge pull request #9892 from JosJuice/jitarm64-flush-temp 
JitArm64: Add temp reg parameter to Arm64RegCache::Flush
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@degasus
degasus committed Jul 22, 2021
2 parents d1beb9e + 302b47f commit 674e2aa
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Showing 5 changed files with 143 additions and 93 deletions.
36 Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View file
@@ -145,8 +145,8 @@ void JitArm64::Shutdown()
void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
{
FlushCarry();
gpr.Flush(FlushMode::All, js.op);
fpr.Flush(FlushMode::All, js.op);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

if (js.op->opinfo->flags & FL_ENDBLOCK)
{
@@ -204,8 +204,8 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
SwitchToFarCode();
SetJumpTarget(handleException);

gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::MaintainState);
gpr.Flush(FlushMode::MaintainState, WA);
fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);

WriteExceptionExit(js.compilerPC, false, true);

@@ -218,8 +218,8 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
void JitArm64::HLEFunction(u32 hook_index)
{
FlushCarry();
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

MOVP2R(ARM64Reg::X8, &HLE::Execute);
MOVI2R(ARM64Reg::W0, js.compilerPC);
@@ -741,8 +741,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
TST(ARM64Reg::W30, LogicalImm(cause_mask, 32));
B(CC_EQ, done_here);

gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::MaintainState);
gpr.Flush(FlushMode::MaintainState, ARM64Reg::W30);
fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);
WriteExceptionExit(js.compilerPC, true, true);
SwitchToNearCode();
SetJumpTarget(no_ext_exception);
@@ -759,6 +759,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
{
ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA);

LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
FixupBranch no_ext_exception = TBZ(WA, IntLog2(EXCEPTION_EXTERNAL_INT));
FixupBranch exception = B();
@@ -775,14 +776,15 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
ProcessorInterface::INT_CAUSE_PE_FINISH;
TST(WA, LogicalImm(cause_mask, 32));
B(CC_EQ, done_here);
gpr.Unlock(WA);

gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::MaintainState);
gpr.Flush(FlushMode::MaintainState, WA);
fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);
WriteExceptionExit(js.compilerPC, true, true);
SwitchToNearCode();
SetJumpTarget(no_ext_exception);
SetJumpTarget(exit);

gpr.Unlock(WA);
}

if (HandleFunctionHooking(op.address))
@@ -801,8 +803,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
SwitchToFarCode();
SetJumpTarget(far_addr);

gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::MaintainState);
gpr.Flush(FlushMode::MaintainState, WA);
fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);

LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, LogicalImm(EXCEPTION_FPU_UNAVAILABLE, 32));
@@ -821,8 +823,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)

if (SConfig::GetInstance().bJITRegisterCacheOff)
{
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
FlushCarry();
}

@@ -855,8 +857,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)

if (code_block.m_broken)
{
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
WriteExit(nextPC);
}

52 Source/Core/Core/PowerPC/JitArm64/JitArm64_Branch.cpp
View file
@@ -18,8 +18,8 @@ void JitArm64::sc(UGeckoInstruction inst)
INSTRUCTION_START
JITDISABLE(bJITBranchOff);

gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

ARM64Reg WA = gpr.GetReg();

@@ -37,8 +37,8 @@ void JitArm64::rfi(UGeckoInstruction inst)
INSTRUCTION_START
JITDISABLE(bJITBranchOff);

gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

// See Interpreter rfi for details
const u32 mask = 0x87C0FFFF;
@@ -95,8 +95,8 @@ void JitArm64::bx(UGeckoInstruction inst)
return;
}

gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

if (js.op->branchIsIdleLoop)
{
@@ -151,20 +151,17 @@ void JitArm64::bcx(UGeckoInstruction inst)
MOVI2R(WA, js.compilerPC + 4);
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF_SPR(SPR_LR));
}
gpr.Unlock(WA);

gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::MaintainState);
gpr.Flush(FlushMode::MaintainState, WA);
fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);

if (js.op->branchIsIdleLoop)
{
// make idle loops go faster
ARM64Reg WA2 = gpr.GetReg();
ARM64Reg XA2 = EncodeRegTo64(WA2);
ARM64Reg XA = EncodeRegTo64(WA);

MOVP2R(XA2, &CoreTiming::Idle);
BLR(XA2);
gpr.Unlock(WA2);
MOVP2R(XA, &CoreTiming::Idle);
BLR(XA);

WriteExceptionExit(js.op->branchTo);
}
@@ -182,10 +179,12 @@ void JitArm64::bcx(UGeckoInstruction inst)

if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, WA);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
WriteExit(js.compilerPC + 4);
}

gpr.Unlock(WA);
}

void JitArm64::bcctrx(UGeckoInstruction inst)
@@ -205,8 +204,8 @@ void JitArm64::bcctrx(UGeckoInstruction inst)
// BO_2 == 1z1zz -> b always

// NPC = CTR & 0xfffffffc;
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);

if (inst.LK_3)
{
@@ -235,7 +234,7 @@ void JitArm64::bclrx(UGeckoInstruction inst)
(inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0;

ARM64Reg WA = gpr.GetReg();
ARM64Reg WB = inst.LK ? gpr.GetReg() : ARM64Reg::INVALID_REG;
ARM64Reg WB = conditional || inst.LK ? gpr.GetReg() : ARM64Reg::INVALID_REG;

FixupBranch pCTRDontBranch;
if ((inst.BO & BO_DONT_DECREMENT_FLAG) == 0) // Decrement and test CTR
@@ -271,11 +270,10 @@ void JitArm64::bclrx(UGeckoInstruction inst)
{
MOVI2R(WB, js.compilerPC + 4);
STR(IndexType::Unsigned, WB, PPC_REG, PPCSTATE_OFF_SPR(SPR_LR));
gpr.Unlock(WB);
}

gpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All);
fpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All);
gpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All, WB);
fpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All, ARM64Reg::INVALID_REG);

if (js.op->branchIsIdleLoop)
{
@@ -292,8 +290,6 @@ void JitArm64::bclrx(UGeckoInstruction inst)
WriteBLRExit(WA);
}

gpr.Unlock(WA);

if (conditional)
SwitchToNearCode();

@@ -304,8 +300,12 @@ void JitArm64::bclrx(UGeckoInstruction inst)

if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{
gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All);
gpr.Flush(FlushMode::All, WA);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
WriteExit(js.compilerPC + 4);
}

gpr.Unlock(WA);
if (WB != ARM64Reg::INVALID_REG)
gpr.Unlock(WB);
}

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