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Merge branch 'JitArmIL' 
This implements a partial JITIL based off of the JIT64IL. It's enough to run most games, albiet at a slow speed.
Implementing instructions for this IL is really simple since it basically is just enabling based on what is already in JIT64IL, and then enabling each individual IL instruction.
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@Sonicadvance1
Sonicadvance1 committed Oct 9, 2013
2 parents cc05f66 + 7bc4838 commit 715d5ae
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Showing 32 changed files with 2,387 additions and 314 deletions.
4 changes: 3 additions & 1 deletion Source/Android/res/values/arrays.xml
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Expand Up @@ -19,10 +19,12 @@
<string-array name="emuCoreEntriesARM" translatable="false">
<item>@string/interpreter</item>
<item>@string/jit_arm_recompiler</item>
<item>@string/jitil_arm_recompiler</item>
</string-array>
<string-array name="emuCoreValuesARM" translatable="false">
<item>0</item>
<item>3</item>
<item>4</item>
</string-array>

<!-- CPU core selection - Other -->
Expand Down Expand Up @@ -137,4 +139,4 @@
<item>4</item>
</string-array>

</resources>
</resources>
1 change: 1 addition & 0 deletions Source/Android/res/values/strings.xml
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Expand Up @@ -69,6 +69,7 @@
<string name="jit64_recompiler">JIT64 Recompiler</string>
<string name="jitil_recompiler">JITIL Recompiler</string>
<string name="jit_arm_recompiler">JIT ARM Recompiler</string>
<string name="jitil_arm_recompiler">JITIL ARM Recompiler</string>
<string name="cpu_core">CPU Core</string>
<string name="cpu_settings">CPU</string>
<string name="emu_core_to_use">Emulation core to use</string>
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15 changes: 4 additions & 11 deletions Source/Core/Common/Src/ArmEmitter.cpp
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Expand Up @@ -491,11 +491,10 @@ void ARMXEmitter::POP(const int num, ...)

void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2)
{
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | op2.Imm5() | (op << 4) | src);
}
void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2)
{
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | (op2 << 8) | (op << 4) | src);
if (op2.GetType() == TYPE_REG)
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | (op2.GetData() << 8) | ((op + 1) << 4) | src);
else
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | op2.Imm5() | (op << 4) | src);
}

// IMM, REG, IMMSREG, RSR
Expand Down Expand Up @@ -610,16 +609,10 @@ void ARMXEmitter::SDIV(ARMReg dest, ARMReg dividend, ARMReg divisor)
}
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, false, dest, src, op2);}
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, true, dest, src, op2);}
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, false, dest, src, op2);}
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, true, dest, src, op2);}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(2, false, dest, src, op2);}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(2, true, dest, src, op2);}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, false, dest, src, op2);}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, true, dest, src, op2);}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(4, false, dest, src, op2);}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(4, true, dest, src, op2);}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, false, dest, src, op2);}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, true, dest, src, op2);}

void ARMXEmitter::MUL (ARMReg dest, ARMReg src, ARMReg op2)
{
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7 changes: 0 additions & 7 deletions Source/Core/Common/Src/ArmEmitter.h
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Expand Up @@ -357,7 +357,6 @@ class ARMXEmitter

void WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 op2, bool RegAdd);
void WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList);
void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2);
void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2);
void WriteSignedMultiply(u32 Op, u32 Op2, u32 Op3, ARMReg dest, ARMReg r1, ARMReg r2);

Expand Down Expand Up @@ -448,17 +447,11 @@ class ARMXEmitter
void ADC (ARMReg dest, ARMReg src, Operand2 op2);
void ADCS(ARMReg dest, ARMReg src, Operand2 op2);
void LSL (ARMReg dest, ARMReg src, Operand2 op2);
void LSL (ARMReg dest, ARMReg src, ARMReg op2);
void LSLS(ARMReg dest, ARMReg src, Operand2 op2);
void LSLS(ARMReg dest, ARMReg src, ARMReg op2);
void LSR (ARMReg dest, ARMReg src, Operand2 op2);
void LSRS(ARMReg dest, ARMReg src, Operand2 op2);
void LSR (ARMReg dest, ARMReg src, ARMReg op2);
void LSRS(ARMReg dest, ARMReg src, ARMReg op2);
void ASR (ARMReg dest, ARMReg src, Operand2 op2);
void ASRS(ARMReg dest, ARMReg src, Operand2 op2);
void ASR (ARMReg dest, ARMReg src, ARMReg op2);
void ASRS(ARMReg dest, ARMReg src, ARMReg op2);
void SBC (ARMReg dest, ARMReg src, Operand2 op2);
void SBCS(ARMReg dest, ARMReg src, Operand2 op2);
void RBIT(ARMReg dest, ARMReg src);
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30 changes: 19 additions & 11 deletions Source/Core/Core/CMakeLists.txt
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Expand Up @@ -166,23 +166,24 @@ set(SRCS Src/ActionReplay.cpp
Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
Src/PowerPC/Interpreter/Interpreter_Tables.cpp
Src/PowerPC/JitCommon/JitBase.cpp
Src/PowerPC/JitCommon/JitCache.cpp)
Src/PowerPC/JitCommon/JitCache.cpp
Src/PowerPC/JitILCommon/IR.cpp
Src/PowerPC/JitILCommon/JitILBase_Branch.cpp
Src/PowerPC/JitILCommon/JitILBase_LoadStore.cpp
Src/PowerPC/JitILCommon/JitILBase_SystemRegisters.cpp
Src/PowerPC/JitILCommon/JitILBase_LoadStoreFloating.cpp
Src/PowerPC/JitILCommon/JitILBase_LoadStorePaired.cpp
Src/PowerPC/JitILCommon/JitILBase_Paired.cpp
Src/PowerPC/JitILCommon/JitILBase_FloatingPoint.cpp
Src/PowerPC/JitILCommon/JitILBase_Integer.cpp
)

if(NOT _M_GENERIC)
set(SRCS ${SRCS}
Src/x64MemTools.cpp
Src/PowerPC/Jit64IL/IR.cpp
Src/PowerPC/Jit64IL/IR_X86.cpp
Src/PowerPC/Jit64IL/JitILAsm.cpp
Src/PowerPC/Jit64IL/JitIL_Branch.cpp
Src/PowerPC/Jit64IL/JitIL.cpp
Src/PowerPC/Jit64IL/JitIL_FloatingPoint.cpp
Src/PowerPC/Jit64IL/JitIL_Integer.cpp
Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp
Src/PowerPC/Jit64IL/JitIL_LoadStoreFloating.cpp
Src/PowerPC/Jit64IL/JitIL_LoadStorePaired.cpp
Src/PowerPC/Jit64IL/JitIL_Paired.cpp
Src/PowerPC/Jit64IL/JitIL_SystemRegisters.cpp
Src/PowerPC/Jit64IL/JitIL_Tables.cpp
Src/PowerPC/Jit64/Jit64_Tables.cpp
Src/PowerPC/Jit64/JitAsm.cpp
Expand Down Expand Up @@ -217,7 +218,14 @@ if(_M_ARM)
Src/PowerPC/JitArm32/JitArm_Paired.cpp
Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp
Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp)
Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
#JitArmIL
Src/PowerPC/JitArmIL/JitIL.cpp
Src/PowerPC/JitArmIL/JitILAsm.cpp
Src/PowerPC/JitArmIL/JitIL_Tables.cpp
Src/PowerPC/JitArmIL/JitIL_Branch.cpp
Src/PowerPC/JitArmIL/IR_Arm.cpp
)
endif()

set(LIBS bdisasm inputcommon videosoftware sfml-network)
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23 changes: 12 additions & 11 deletions Source/Core/Core/Core.vcxproj
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Expand Up @@ -352,18 +352,18 @@
<ClCompile Include="Src\PowerPC\Interpreter\Interpreter_Paired.cpp" />
<ClCompile Include="Src\PowerPC\Interpreter\Interpreter_SystemRegisters.cpp" />
<ClCompile Include="Src\PowerPC\Interpreter\Interpreter_Tables.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\IR.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\IR.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_Branch.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_FloatingPoint.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_Integer.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_LoadStore.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_LoadStoreFloating.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_LoadStorePaired.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_Paired.cpp" />
<ClCompile Include="Src\PowerPC\JitILCommon\JitILBase_SystemRegisters.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\IR_X86.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitILAsm.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_Branch.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_FloatingPoint.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_Integer.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_LoadStore.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_LoadStoreFloating.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_LoadStorePaired.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_Paired.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_SystemRegisters.cpp" />
<ClCompile Include="Src\PowerPC\Jit64IL\JitIL_Tables.cpp" />
<ClCompile Include="Src\PowerPC\Jit64\Jit.cpp" />
<ClCompile Include="Src\PowerPC\Jit64\Jit64_Tables.cpp" />
Expand Down Expand Up @@ -560,14 +560,15 @@
<ClInclude Include="Src\PowerPC\Interpreter\Interpreter.h" />
<ClInclude Include="Src\PowerPC\Interpreter\Interpreter_FPUtils.h" />
<ClInclude Include="Src\PowerPC\Interpreter\Interpreter_Tables.h" />
<ClInclude Include="Src\PowerPC\Jit64IL\IR.h" />
<ClInclude Include="Src\PowerPC\Jit64IL\JitIL.h" />
<ClInclude Include="Src\PowerPC\Jit64IL\JitILAsm.h" />
<ClInclude Include="Src\PowerPC\Jit64IL\JitIL_Tables.h" />
<ClInclude Include="Src\PowerPC\Jit64\Jit.h" />
<ClInclude Include="Src\PowerPC\Jit64\Jit64_Tables.h" />
<ClInclude Include="Src\PowerPC\Jit64\JitAsm.h" />
<ClInclude Include="Src\PowerPC\Jit64\JitRegCache.h" />
<ClInclude Include="Src\PowerPC\JitILCommon\IR.h" />
<ClInclude Include="Src\PowerPC\JitILCommon\JitILBase.h" />
<ClInclude Include="Src\PowerPC\JitCommon\JitAsmCommon.h" />
<ClInclude Include="Src\PowerPC\JitCommon\JitBackpatch.h" />
<ClInclude Include="Src\PowerPC\JitCommon\JitBase.h" />
Expand Down Expand Up @@ -611,4 +612,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>
</Project>
2 changes: 1 addition & 1 deletion Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
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Expand Up @@ -24,7 +24,7 @@ The register allocation is linear scan allocation.
#pragma warning(disable:4146) // unary minus operator applied to unsigned type, result still unsigned
#endif

#include "IR.h"
#include "../JitILCommon/IR.h"
#include "../PPCTables.h"
#include "../../CoreTiming.h"
#include "../../HW/Memmap.h"
Expand Down
106 changes: 11 additions & 95 deletions Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.h
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Expand Up @@ -24,7 +24,8 @@
#include "../JitCommon/Jit_Util.h"
#include "x64Emitter.h"
#include "x64Analyzer.h"
#include "IR.h"
#include "../JitILCommon/JitILBase.h"
#include "../JitILCommon/IR.h"
#include "../JitCommon/JitBase.h"
#include "JitILAsm.h"

Expand All @@ -44,10 +45,11 @@
#define DISABLE64
#endif

class JitIL : public Jitx86Base
class JitIL : public JitILBase, public EmuCodeBlock
{
private:

JitBlockCache blocks;
TrampolineCache trampolines;

// The default code buffer. We keep it around to not have to alloc/dealloc a
// large chunk of memory for each recompiled block.
Expand All @@ -73,6 +75,12 @@ class JitIL : public Jitx86Base

void Trace();

JitBlockCache *GetBlockCache() { return &blocks; }

const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx) { return NULL; };

bool IsInCodeSpace(u8 *ptr) { return IsInSpace(ptr); }

void ClearCache();
const u8 *GetDispatcher() {
return asm_routines.dispatcher; // asm_routines.dispatcher
Expand Down Expand Up @@ -125,98 +133,6 @@ class JitIL : public Jitx86Base
void DynaRunTable31(UGeckoInstruction _inst);
void DynaRunTable59(UGeckoInstruction _inst);
void DynaRunTable63(UGeckoInstruction _inst);

void addx(UGeckoInstruction inst);
void boolX(UGeckoInstruction inst);
void mulli(UGeckoInstruction inst);
void mulhwux(UGeckoInstruction inst);
void mullwx(UGeckoInstruction inst);
void divwux(UGeckoInstruction inst);
void srawix(UGeckoInstruction inst);
void srawx(UGeckoInstruction inst);
void addex(UGeckoInstruction inst);
void addzex(UGeckoInstruction inst);

void extsbx(UGeckoInstruction inst);
void extshx(UGeckoInstruction inst);

void sc(UGeckoInstruction _inst);
void rfi(UGeckoInstruction _inst);

void bx(UGeckoInstruction inst);
void bclrx(UGeckoInstruction _inst);
void bcctrx(UGeckoInstruction _inst);
void bcx(UGeckoInstruction inst);

void mtspr(UGeckoInstruction inst);
void mfspr(UGeckoInstruction inst);
void mtmsr(UGeckoInstruction inst);
void mfmsr(UGeckoInstruction inst);
void mftb(UGeckoInstruction inst);
void mtcrf(UGeckoInstruction inst);
void mfcr(UGeckoInstruction inst);
void mcrf(UGeckoInstruction inst);
void crXX(UGeckoInstruction inst);

void reg_imm(UGeckoInstruction inst);

void ps_sel(UGeckoInstruction inst);
void ps_mr(UGeckoInstruction inst);
void ps_sign(UGeckoInstruction inst); //aggregate
void ps_arith(UGeckoInstruction inst); //aggregate
void ps_mergeXX(UGeckoInstruction inst);
void ps_maddXX(UGeckoInstruction inst);
void ps_rsqrte(UGeckoInstruction inst);
void ps_sum(UGeckoInstruction inst);
void ps_muls(UGeckoInstruction inst);

void fp_arith_s(UGeckoInstruction inst);

void fcmpx(UGeckoInstruction inst);
void fmrx(UGeckoInstruction inst);

void cmpXX(UGeckoInstruction inst);

void cntlzwx(UGeckoInstruction inst);

void lfs(UGeckoInstruction inst);
void lfd(UGeckoInstruction inst);
void stfd(UGeckoInstruction inst);
void stfs(UGeckoInstruction inst);
void stfsx(UGeckoInstruction inst);
void psq_l(UGeckoInstruction inst);
void psq_st(UGeckoInstruction inst);

void fmaddXX(UGeckoInstruction inst);
void fsign(UGeckoInstruction inst);
void stX(UGeckoInstruction inst); //stw sth stb
void lXz(UGeckoInstruction inst);
void lbzu(UGeckoInstruction inst);
void lha(UGeckoInstruction inst);
void rlwinmx(UGeckoInstruction inst);
void rlwimix(UGeckoInstruction inst);
void rlwnmx(UGeckoInstruction inst);
void negx(UGeckoInstruction inst);
void slwx(UGeckoInstruction inst);
void srwx(UGeckoInstruction inst);
void dcbst(UGeckoInstruction inst);
void dcbz(UGeckoInstruction inst);
void lfsx(UGeckoInstruction inst);

void subfic(UGeckoInstruction inst);
void subfcx(UGeckoInstruction inst);
void subfx(UGeckoInstruction inst);
void subfex(UGeckoInstruction inst);

void lXzx(UGeckoInstruction inst);
void lhax(UGeckoInstruction inst);

void stXx(UGeckoInstruction inst);

void lmw(UGeckoInstruction inst);
void stmw(UGeckoInstruction inst);

void icbi(UGeckoInstruction inst);
};

void Jit(u32 em_address);
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