Fix JIT from rebasing on PPSSPP ArmEmitter.

dolphin-emu · Mar 12, 2013 · 8406d99 · 8406d99
1 parent b94b4a9
commit 8406d99
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Showing 6 changed files with 12 additions and 9 deletions.
diff --git a/Source/Core/Common/Src/ArmEmitter.cpp b/Source/Core/Common/Src/ArmEmitter.cpp
@@ -616,7 +616,7 @@ void ARMXEmitter::WriteStoreOp(u32 op, ARMReg src, ARMReg dest, s16 op2)
        bool Index = true;
        bool Add = op2 >= 0 ? true : false;
        u32 imm = abs(op2);
-       Write32(condition | (op << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (src << 12) | imm);
+       Write32(condition | (op << 20) | (Index << 24) | (Add << 23) | (src << 16) | (dest << 12) | imm);
 }
 void ARMXEmitter::STR  (ARMReg result, ARMReg base, s16 op) { WriteStoreOp(0x40, base, result, op);}
 void ARMXEmitter::STRH (ARMReg result, ARMReg base, Operand2 op)

diff --git a/Source/Core/Common/Src/ArmEmitter.h b/Source/Core/Common/Src/ArmEmitter.h
@@ -497,7 +497,7 @@ class ARMXEmitter
 	// Memory load/store operations
 	void LDR  (ARMReg dest, ARMReg src, s16 op2 = 0);
 	void LDRH (ARMReg dest, ARMReg src, Operand2 op2 = 0);
-	void LDRSH(ARMReg dest, ARMReg src, s16 op2 = 0);
+	void LDRSH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
 	void LDRB (ARMReg dest, ARMReg src, s16 op2 = 0);
 	void LDRSB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
 	// Offset adds to the base register in LDR

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
@@ -361,8 +361,9 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 	// Downcount flag check, Only valid for linked blocks
 	{
 		FixupBranch skip = B_CC(CC_PL);
-		ARMABI_MOVI2M((u32)&PC, js.blockStart);
 		ARMReg rA = gpr.GetReg(false);
+		MOVI2R(rA, js.blockStart);
+		STR(rA, R9, PPCSTATE_OFF(pc));
 		MOVI2R(rA, (u32)asm_routines.doTiming);
 		B(rA);
 		SetJumpTarget(skip);

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp
@@ -23,6 +23,7 @@
 // locating performance issues.
 
 #include "../JitInterface.h"
+#include "Jit.h"
 #include "JitArmCache.h"
 
 

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Branch.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Branch.cpp
@@ -48,8 +48,9 @@ void JitArm::sc(UGeckoInstruction inst)
 	gpr.Flush();
 	fpr.Flush();
 
-	ARMABI_MOVI2M((u32)&PC, js.compilerPC + 4); // Destroys R12 and R14
 	ARMReg rA = gpr.GetReg();
+	MOVI2R(rA, js.compilerPC + 4);
+	STR(rA, R9, PPCSTATE_OFF(pc));
 	LDR(rA, R9, PPCSTATE_OFF(Exceptions));
 	ORR(rA, rA, EXCEPTION_SYSCALL);
 	STR(rA, R9, PPCSTATE_OFF(Exceptions));

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -40,7 +40,7 @@ void JitArm::GenerateRC(int cr) {
 	SetCC(CC_MI); MOV(rB, 0x8); // Result < 0
 	SetCC();
 
-	STRB(R9, rB, PPCSTATE_OFF(cr_fast) + cr);
+	STRB(rB, R9, PPCSTATE_OFF(cr_fast) + cr);
 	gpr.Unlock(rB);
 }
 void JitArm::ComputeRC(int cr) {
@@ -51,7 +51,7 @@ void JitArm::ComputeRC(int cr) {
 	SetCC(CC_GT); MOV(rB, 0x4); // Result > 0
 	SetCC();
 
-	STRB(R9, rB, PPCSTATE_OFF(cr_fast) + cr);
+	STRB(rB, R9, PPCSTATE_OFF(cr_fast) + cr);
 	gpr.Unlock(rB);
 }
 
@@ -232,7 +232,7 @@ void JitArm::cmpli(UGeckoInstruction inst)
 	SetCC(CC_HI); MOV(rA, 0x4); // Result > 0
 	SetCC();
 
-	STRB(R9, rA, PPCSTATE_OFF(cr_fast) + crf);
+	STRB(rA, R9, PPCSTATE_OFF(cr_fast) + crf);
 	gpr.Unlock(rA);
 
 }
@@ -269,7 +269,7 @@ void JitArm::rlwimix(UGeckoInstruction inst)
 	ARMReg rB = gpr.GetReg();
 	MOVI2R(rA, mask);
 
-	Operand2 Shift(32 - inst.SH, ST_ROR, RS); // This rotates left, while ARM has only rotate right, so swap it.
+	Operand2 Shift(RS, ST_ROR, 32 - inst.SH); // This rotates left, while ARM has only rotate right, so swap it.
 	if (inst.Rc)
 	{
 		BIC (rB, RA, rA); // RA & ~mask
@@ -296,7 +296,7 @@ void JitArm::rlwinmx(UGeckoInstruction inst)
 	ARMReg rA = gpr.GetReg();
 	MOVI2R(rA, mask);
 
-	Operand2 Shift(32 - inst.SH, ST_ROR, RS); // This rotates left, while ARM has only rotate right, so swap it.
+	Operand2 Shift(RS, ST_ROR, 32 - inst.SH); // This rotates left, while ARM has only rotate right, so swap it.
 	if (inst.Rc)
 	{
 		ANDS(RA, rA, Shift);