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Jit_LoadStore: stmw

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MerryMage committed Oct 15, 2018
1 parent 98cf0b3 commit 9438ea0ef566a80e1db7152e01e8e7a9ce724b3d
Showing with 14 additions and 13 deletions.
  1. +14 −13 Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
@@ -533,26 +533,27 @@ void Jit64::stmw(UGeckoInstruction inst)
INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff);
int a = inst.RA, d = inst.RD;
// TODO: This doesn't handle rollback on DSI correctly
for (int i = inst.RD; i < 32; i++)
for (int i = d; i < 32; i++)
{
if (inst.RA)
MOV(32, R(RSCRATCH), gpr.R(inst.RA));
else
RCOpArg Ra = a ? gpr.Use(a, RCMode::Read) : RCOpArg::Imm32(0);
RCOpArg Ri = gpr.Use(i, RCMode::Read);
RegCache::Realize(Ra, Ri);
if (Ra.IsZero())
XOR(32, R(RSCRATCH), R(RSCRATCH));
if (gpr.R(i).IsImm())
{
SafeWriteRegToReg(gpr.R(i), RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16,
CallerSavedRegistersInUse());
}
else
MOV(32, R(RSCRATCH), Ra);
if (!Ri.IsImm())
{
MOV(32, R(RSCRATCH2), gpr.R(i));
SafeWriteRegToReg(RSCRATCH2, RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16,
CallerSavedRegistersInUse());
MOV(32, R(RSCRATCH2), Ri);
Ri = RCOpArg::R(RSCRATCH2);
}
SafeWriteRegToReg(Ri, RSCRATCH, 32, (i - d) * 4 + (u32)(s32)inst.SIMM_16,
CallerSavedRegistersInUse());
}
gpr.UnlockAllX();
}
void Jit64::eieio(UGeckoInstruction inst)

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