[ARM] ps_sel implementation.

dolphin-emu · Sep 16, 2013 · 98fb4c1 · 98fb4c1
1 parent cba2dd0
commit 98fb4c1
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Showing 3 changed files with 41 additions and 1 deletion.
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
@@ -240,6 +240,7 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
 	void ps_abs(UGeckoInstruction _inst);
 	void ps_nabs(UGeckoInstruction _inst);
 	void ps_rsqrte(UGeckoInstruction _inst);
+	void ps_sel(UGeckoInstruction _inst);
 
 	// LoadStore paired
 	void psq_l(UGeckoInstruction _inst);

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Paired.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Paired.cpp
@@ -90,6 +90,45 @@ void JitArm::ps_rsqrte(UGeckoInstruction inst)
 	gpr.Unlock(fpscrReg, rA);
 }
 
+void JitArm::ps_sel(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(bJITPairedOff)
+
+	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
+
+	if (inst.Rc) {
+		Default(inst); return;
+	}
+	ARMReg vA0 = fpr.R0(a);
+	ARMReg vA1 = fpr.R1(a);
+	ARMReg vB0 = fpr.R0(b);
+	ARMReg vB1 = fpr.R1(b);
+	ARMReg vC0 = fpr.R0(c);
+	ARMReg vC1 = fpr.R1(c);
+	ARMReg vD0 = fpr.R0(d, false);
+	ARMReg vD1 = fpr.R1(d, false);
+
+	VCMP(vA0);
+	VMRS(_PC);
+
+	FixupBranch GT0 = B_CC(CC_GE);
+	VMOV(vD0, vB0);
+	FixupBranch EQ0 = B();
+	SetJumpTarget(GT0);
+	VMOV(vD0, vC0);
+	SetJumpTarget(EQ0);
+
+	VCMP(vA1);
+	VMRS(_PC);
+	FixupBranch GT1 = B_CC(CC_GE);
+	VMOV(vD1, vB1);
+	FixupBranch EQ1 = B();
+	SetJumpTarget(GT1);
+	VMOV(vD1, vC1);
+	SetJumpTarget(EQ1);
+}
+
 void JitArm::ps_add(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
@@ -152,7 +152,7 @@ static GekkoOPTemplate table4_2[] =
 	{18, &JitArm::Default}, //"ps_div",    OPTYPE_PS, 0, 16}},
 	{20, &JitArm::ps_sub}, //"ps_sub",    OPTYPE_PS, 0}},
 	{21, &JitArm::ps_add}, //"ps_add",    OPTYPE_PS, 0}},
-	{23, &JitArm::Default}, //"ps_sel",    OPTYPE_PS, 0}},
+	{23, &JitArm::ps_sel}, //"ps_sel",    OPTYPE_PS, 0}},
 	{24, &JitArm::Default}, //"ps_res",    OPTYPE_PS, 0}},
 	{25, &JitArm::ps_mul}, //"ps_mul",    OPTYPE_PS, 0}},
 	{26, &JitArm::ps_rsqrte}, //"ps_rsqrte", OPTYPE_PS, 0, 1}},