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Interpreter_FloatingPoint: Don't store to destination in fres if VE o…

…r ZE is set and a relevant exception occurs

In the PowerPC Microprocessor Family: The Programming Environments
Manual for 32 and 64-bit Microprocessors, in section 3.3.6.1, Table
3-12 lists what should occur if an invalid operation exception occurs in
situations where VE is set and when VE is not set. In the case where VE
is set, it lists the frD as "Unchanged". It also lists the FPRF flags as
"Unchanged".

Further down in Table 3-13, the listings for what should occur when zero
divide exceptions occur is listed, both for when ZE is set, and when it
isn't. When ZE is set, it lists frD as "Unchanged". It also lists the
FPRF flags as "Unchanged" as well.

This also alters the code so that we don't even calculate the result if
we don't need to compute it, making it a little bit less wasteful.
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lioncash committed Jun 1, 2018
1 parent fcae279 commit a08ad82ace064f961b13369c96a0f3b48ca7ca5c
Showing with 8 additions and 5 deletions.
  1. +8 −5 Source/Core/Core/PowerPC/Interpreter/Interpreter_FloatingPoint.cpp
@@ -387,27 +387,30 @@ void Interpreter::fdivsx(UGeckoInstruction inst)
void Interpreter::fresx(UGeckoInstruction inst)
{
const double b = rPS0(inst.FB);
const double result = Common::ApproximateReciprocal(b);
rPS0(inst.FD) = rPS1(inst.FD) = result;
const auto compute_result = [inst](double value) {
const double result = Common::ApproximateReciprocal(value);
rPS0(inst.FD) = rPS1(inst.FD) = result;
PowerPC::UpdateFPRF(result);
};
if (b == 0.0)
{
SetFPException(FPSCR_ZX);
if (FPSCR.ZE == 0)
PowerPC::UpdateFPRF(result);
compute_result(b);
}
else if (Common::IsSNAN(b))
{
SetFPException(FPSCR_VXSNAN);
if (FPSCR.VE == 0)
PowerPC::UpdateFPRF(result);
compute_result(b);
}
else
{
PowerPC::UpdateFPRF(result);
compute_result(b);
}
if (inst.Rc)

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