[ARM] Disable mfmsr. Implement stb and subfx.

dolphin-emu · Jul 17, 2013 · b30a697 · b30a697
1 parent 5899013
commit b30a697
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Showing 5 changed files with 68 additions and 3 deletions.
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
@@ -157,6 +157,7 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
 	void orx(UGeckoInstruction _inst);
 	void rlwimix(UGeckoInstruction _inst);
 	void rlwinmx(UGeckoInstruction _inst);
+	void subfx(UGeckoInstruction _inst);
 	void extshx(UGeckoInstruction inst);
 	void extsbx(UGeckoInstruction inst);
 
@@ -173,6 +174,7 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
 	void lhz(UGeckoInstruction _inst);
 	void lwz(UGeckoInstruction _inst);
 	void lwzx(UGeckoInstruction _inst);
+	void stb(UGeckoInstruction _inst);
 	void stbu(UGeckoInstruction _inst);
 	void sth(UGeckoInstruction _inst);
 	void sthu(UGeckoInstruction _inst);

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -99,6 +99,18 @@ void JitArm::addx(UGeckoInstruction inst)
 	ADDS(RD, RA, RB);
 	if (inst.Rc) ComputeRC();
 }
+void JitArm::subfx(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(Integer)
+
+	ARMReg RA = gpr.R(inst.RA);
+	ARMReg RB = gpr.R(inst.RB);
+	ARMReg RD = gpr.R(inst.RD);
+	SUBS(RD, RB, RA);
+	if (inst.OE) PanicAlert("OE: subfx");
+	if (inst.Rc) GenerateRC();
+}
 void JitArm::mulli(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
@@ -36,6 +36,55 @@
 #else
 #define FASTMEM 0
 #endif
+void JitArm::stb(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(LoadStore)
+
+	ARMReg RS = gpr.R(inst.RS);
+#if 0 // FASTMEM
+	// R10 contains the dest address
+	ARMReg Value = R11;
+	ARMReg RA;
+	if (inst.RA)
+		RA = gpr.R(inst.RA);
+	MOV(Value, RS);
+	if (inst.RA)
+	{
+		MOVI2R(R10, inst.SIMM_16, false);
+		ADD(R10, R10, RA);
+	}
+	else
+	{
+		MOVI2R(R10, (u32)inst.SIMM_16, false);
+		NOP(1);
+	}
+	StoreFromReg(R10, Value, 16, 0);
+#else
+	ARMReg ValueReg = gpr.GetReg();
+	ARMReg Addr = gpr.GetReg();
+	ARMReg Function = gpr.GetReg();
+
+	MOV(ValueReg, RS);
+	if (inst.RA)
+	{
+		MOVI2R(Addr, inst.SIMM_16);
+		ARMReg RA = gpr.R(inst.RA);
+		ADD(Addr, Addr, RA);
+	}
+	else
+		MOVI2R(Addr, (u32)inst.SIMM_16);
+
+	MOVI2R(Function, (u32)&Memory::Write_U8);	
+	PUSH(4, R0, R1, R2, R3);
+	MOV(R0, ValueReg);
+	MOV(R1, Addr);
+	BL(Function);
+	POP(4, R0, R1, R2, R3);
+	gpr.Unlock(ValueReg, Addr, Function);
+#endif
+}
+
 void JitArm::stbu(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
@@ -111,6 +111,8 @@ void JitArm::mfmsr(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(SystemRegisters)
-
+	Default(inst); return;
+
 	LDR(gpr.R(inst.RD), R9, PPCSTATE_OFF(msr));
 }
+
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
@@ -91,7 +91,7 @@ static GekkoOPTemplate primarytable[] =
 	{45, &JitArm::sthu}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
 	{36, &JitArm::stw}, //"stw",  OPTYPE_STORE, FL_IN_A | FL_IN_S}},
 	{37, &JitArm::stwu}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
-	{38, &JitArm::Default}, //"stb",  OPTYPE_STORE, FL_IN_A | FL_IN_S}},
+	{38, &JitArm::stb}, //"stb",  OPTYPE_STORE, FL_IN_A | FL_IN_S}},
 	{39, &JitArm::stbu}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
 
 	{46, &JitArm::Default}, //"lmw",   OPTYPE_SYSTEM, FL_EVIL, 10}},
@@ -322,7 +322,7 @@ static GekkoOPTemplate table31_2[] =
 	{235,  &JitArm::Default}, //"mullwx",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
 	{747,  &JitArm::Default}, //"mullwox",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
 	{104,  &JitArm::negx}, //"negx",    OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
-	{40,   &JitArm::Default}, //"subfx",   OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
+	{40,   &JitArm::subfx}, //"subfx",   OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
 	{552,  &JitArm::Default}, //"subox",   OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
 	{8,    &JitArm::Default}, //"subfcx",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
 	{136,  &JitArm::Default}, //"subfex",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},