[ARM] Add mullwx, mulhwux and half implemented srawix instructions. C…

…hange fsubsx/fmulsx slightly, still broken.
dolphin-emu · Aug 19, 2013 · b4baa4f · b4baa4f
1 parent 9bded13
commit b4baa4f
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Showing 4 changed files with 87 additions and 9 deletions.
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
@@ -156,6 +156,8 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
 	void cmpli(UGeckoInstruction _inst);
 	void negx(UGeckoInstruction _inst);
 	void mulli(UGeckoInstruction _inst);
+	void mullwx(UGeckoInstruction _inst);
+	void mulhwux(UGeckoInstruction _inst);
 	void ori(UGeckoInstruction _inst);	
 	void oris(UGeckoInstruction _inst);	
 	void orx(UGeckoInstruction _inst);
@@ -166,6 +168,7 @@ class JitArm : public JitBase, public ArmGen::ARMXCodeBlock
 	void rlwimix(UGeckoInstruction _inst);
 	void rlwinmx(UGeckoInstruction _inst);
 	void subfx(UGeckoInstruction _inst);
+	void srawix(UGeckoInstruction _inst);
 	void extshx(UGeckoInstruction inst);
 	void extsbx(UGeckoInstruction inst);
 

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_FloatingPoint.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_FloatingPoint.cpp
@@ -87,13 +87,13 @@ void JitArm::fsubsx(UGeckoInstruction inst)
 
 	Default(inst); return;
 
-	ARMReg vD0 = fpr.R0(inst.FD);
-	ARMReg vD1 = fpr.R1(inst.FD);
 	ARMReg vA = fpr.R0(inst.FA);
 	ARMReg vB = fpr.R0(inst.FB);
+	ARMReg vD0 = fpr.R0(inst.FD);
+	ARMReg vD1 = fpr.R1(inst.FD);
 
 	VSUB(vD0, vA, vB);
-	VSUB(vD1, vA, vB);
+	VMOV(vD1, vD0);
 	if (inst.Rc) Helper_UpdateCR1(vD0);
 }
 
@@ -117,13 +117,13 @@ void JitArm::fmulsx(UGeckoInstruction inst)
 
 	Default(inst); return;
 
-	ARMReg vD0 = fpr.R0(inst.FD);
-	ARMReg vD1 = fpr.R1(inst.FD);
 	ARMReg vA = fpr.R0(inst.FA);
 	ARMReg vC = fpr.R0(inst.FC);
+	ARMReg vD0 = fpr.R0(inst.FD);
+	ARMReg vD1 = fpr.R1(inst.FD);
 
 	VMUL(vD0, vA, vC);
-	VMUL(vD1, vA, vC);
+	VMOV(vD1, vD0);
 	if (inst.Rc) Helper_UpdateCR1(vD0);
 }
 void JitArm::fmulx(UGeckoInstruction inst)

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -239,6 +239,36 @@ void JitArm::mulli(UGeckoInstruction inst)
 	gpr.Unlock(rA);
 }
 
+void JitArm::mullwx(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(Integer)
+
+	u32 a = inst.RA, b = inst.RB, d = inst.RD;
+
+	ARMReg RA = gpr.R(a);
+	ARMReg RB = gpr.R(b);
+	ARMReg RD = gpr.R(d);
+	MULS(RD, RA, RB);
+	if (inst.OE) PanicAlert("OE: mullwx");
+	if (inst.Rc) ComputeRC();
+}
+
+void JitArm::mulhwux(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(Integer)
+
+	u32 a = inst.RA, b = inst.RB, d = inst.RD;
+
+	ARMReg RA = gpr.R(a);
+	ARMReg RB = gpr.R(b);
+	ARMReg RD = gpr.R(d);
+	ARMReg rA = gpr.GetReg(false);
+	UMULLS(rA, RD, RA, RB);
+	if (inst.Rc) ComputeRC();
+}
+
 void JitArm::ori(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
@@ -583,4 +613,49 @@ void JitArm::rlwinmx(UGeckoInstruction inst)
 
 	//m_GPR[inst.RA] = _rotl(m_GPR[inst.RS],inst.SH) & mask;
 }
+void JitArm::srawix(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(Integer)
+	int a = inst.RA;
+	int s = inst.RS;
+	int amount = inst.SH;
+	if (amount != 0)
+	{
+		Default(inst); return;
+		ARMReg RA = gpr.R(a);
+		ARMReg RS = gpr.R(s);
+		ARMReg tmp = gpr.GetReg();
+		Operand2 mask = Operand2(2, 2); // XER_CA_MASK
+
+		MOV(tmp, RS);
+		ASRS(RA, RS, amount);
+		if (inst.Rc)
+			GenerateRC();
+		LSL(tmp, tmp, 32 - amount);
+		TST(tmp, RA);
+
+		LDR(tmp, R9, PPCSTATE_OFF(spr[SPR_XER]));
+		BIC(tmp, tmp, mask);
+		SetCC(CC_EQ);
+		ORR(tmp, tmp, mask);
+		SetCC();
+		STR(tmp, R9, PPCSTATE_OFF(spr[SPR_XER]));
+		gpr.Unlock(tmp);
+	}
+	else
+	{
+		ARMReg RA = gpr.R(a);
+		ARMReg RS = gpr.R(s);
+		MOV(RA, RS);
+
+		ARMReg tmp = gpr.GetReg();
+		Operand2 mask = Operand2(2, 2); // XER_CA_MASK
+		LDR(tmp, R9, PPCSTATE_OFF(spr[SPR_XER]));
+		BIC(tmp, tmp, mask);
+		STR(tmp, R9, PPCSTATE_OFF(spr[SPR_XER]));
+		gpr.Unlock(tmp);
+
+	}
+}
 
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
@@ -209,7 +209,7 @@ static GekkoOPTemplate table31[] =
 	{954, &JitArm::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
 	{536, &JitArm::Default}, //"srwx",   OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
 	{792, &JitArm::Default}, //"srawx",  OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
-	{824, &JitArm::Default}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
+	{824, &JitArm::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
 	{24,  &JitArm::Default}, //"slwx",   OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
 
 	{54,   &JitArm::dcbst}, //"dcbst",  OPTYPE_DCACHE, 0, 4}},
@@ -318,8 +318,8 @@ static GekkoOPTemplate table31_2[] =
 	{459,  &JitArm::Default}, //"divwux",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
 	{971,  &JitArm::Default}, //"divwuox",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
 	{75,   &JitArm::Default}, //"mulhwx",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
-	{11,   &JitArm::Default}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
-	{235,  &JitArm::Default}, //"mullwx",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
+	{11,   &JitArm::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
+	{235,  &JitArm::mullwx}, //"mullwx",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
 	{747,  &JitArm::Default}, //"mullwox",  OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
 	{104,  &JitArm::negx}, //"negx",    OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
 	{40,   &JitArm::subfx}, //"subfx",   OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},