[ARM] Missed flushing our register caches in mtmsr. This would cause …

…a buttload of problems, including the suspected ori being wrong issue. So flush caches and reenable ori.
dolphin-emu · Aug 5, 2013 · db93b51 · db93b51
1 parent bafed34
commit db93b51
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Showing 2 changed files with 6 additions and 3 deletions.
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -123,12 +123,11 @@ void JitArm::mulli(UGeckoInstruction inst)
 	MUL(RD, RA, rA);
 	gpr.Unlock(rA);
 }
-// Wrong 04-08-2013. Breaks Wind Waker booting
+
 void JitArm::ori(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(Integer)
-	Default(inst); return;
 
 	ARMReg RA = gpr.R(inst.RA);
 	ARMReg RS = gpr.R(inst.RS);
@@ -283,7 +282,7 @@ void JitArm::cmpli(UGeckoInstruction inst)
 	gpr.Unlock(rA);
 
 }
-// Wrong - 27/10/2012
+
 void JitArm::negx(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
@@ -105,6 +105,10 @@ void JitArm::mtmsr(UGeckoInstruction inst)
 	//JITDISABLE(SystemRegisters)
 
 	STR(gpr.R(inst.RS), R9, PPCSTATE_OFF(msr));
+
+	gpr.Flush();
+	fpr.Flush();
+
 	WriteExit(js.compilerPC + 4, 0);
 }
 void JitArm::mfmsr(UGeckoInstruction inst)