Merge pull request #8551 from Sintendo/jit64addx

Jit64: addx optimizations
dolphin-emu · Jan 6, 2020 · f17f03e · f17f03e
2 parents 6e18dfb + 12fcbac
commit f17f03e
Showing 1 changed file with 15 additions and 4 deletions.
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
@@ -1330,18 +1330,29 @@ void Jit64::addx(UGeckoInstruction inst)
     RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
     RegCache::Realize(Ra, Rb, Rd);
 
-    if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
+    if (d == a)
     {
-      LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
+      ADD(32, Rd, Rb);
     }
     else if (d == b)
     {
       ADD(32, Rd, Ra);
     }
+    else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
+    {
+      LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
+    }
+    else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
+    {
+      LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
+    }
+    else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
+    {
+      LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
+    }
     else
     {
-      if (d != a)
-        MOV(32, Rd, Ra);
+      MOV(32, Rd, Ra);
       ADD(32, Rd, Rb);
     }
     if (inst.OE)