90 changes: 49 additions & 41 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Branch.cpp
View file
Expand Up @@ -50,9 +50,9 @@ void JitArm::sc(UGeckoInstruction inst)

ARMABI_MOVI2M((u32)&PC, js.compilerPC + 4); // Destroys R12 and R14
ARMReg rA = gpr.GetReg();
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
ORR(rA, rA, EXCEPTION_SYSCALL);
STR(R9, rA, STRUCT_OFF(PowerPC::ppcState, Exceptions));
STR(R9, rA, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
gpr.Unlock(rA);

WriteExceptionExit();
Expand All @@ -78,25 +78,22 @@ void JitArm::rfi(UGeckoInstruction inst)
ARMReg rB = gpr.GetReg();
ARMReg rC = gpr.GetReg();
ARMReg rD = gpr.GetReg();
MOVI2R(rA, (u32)&MSR);
MOVI2R(rB, (~mask) & clearMSR13);
MOVI2R(rC, mask & clearMSR13);

LDR(rD, rA);
LDR(rD, R9, PPCSTATE_OFF(PowerPC::ppcState, msr));

AND(rD, rD, rB); // rD = Masked MSR
STR(rA, rD);
STR(R9, rD, PPCSTATE_OFF(PowerPC::ppcState, msr));

MOVI2R(rB, (u32)&SRR1);
LDR(rB, rB); // rB contains SRR1 here
LDR(rB, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_SRR1])); // rB contains SRR1 here

AND(rB, rB, rC); // rB contains masked SRR1 here
ORR(rB, rD, rB); // rB = Masked MSR OR masked SRR1

STR(rA, rB); // STR rB in to rA
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, msr)); // STR rB in to rA

MOVI2R(rA, (u32)&SRR0);
LDR(rA, rA);
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_SRR0]));

gpr.Unlock(rB, rC, rD);
WriteRfiExitDestInR(rA); // rA gets unlocked here
Expand All @@ -116,8 +113,13 @@ void JitArm::bx(UGeckoInstruction inst)
// We must always process the following sentence
// even if the blocks are merged by PPCAnalyst::Flatten().
if (inst.LK)
ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);

{
ARMReg rA = gpr.GetReg(false);
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rA, Jumpto);
STR(R9, rA, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
//ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
}
// If this is not the last instruction of a block,
// we will skip the rest process.
// Because PPCAnalyst::Flatten() merged the blocks.
Expand Down Expand Up @@ -164,10 +166,9 @@ void JitArm::bcx(UGeckoInstruction inst)
FixupBranch pCTRDontBranch;
if ((inst.BO & BO_DONT_DECREMENT_FLAG) == 0) // Decrement and test CTR
{
MOVI2R(rA, (u32)&CTR);
LDR(rB, rA);
LDR(rB, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));
SUBS(rB, rB, 1);
STR(rA, rB);
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));

//SUB(32, M(&CTR), Imm8(1));
if (inst.BO & BO_BRANCH_IF_CTR_0)
Expand All @@ -179,7 +180,7 @@ void JitArm::bcx(UGeckoInstruction inst)
FixupBranch pConditionDontBranch;
if ((inst.BO & BO_DONT_CHECK_CONDITION) == 0) // Test a CR bit
{
LDRB(rA, R9, STRUCT_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
LDRB(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
TST(rA, 8 >> (inst.BI & 3));

//TEST(8, M(&PowerPC::ppcState.cr_fast[inst.BI >> 2]), Imm8(8 >> (inst.BI & 3)));
Expand All @@ -188,10 +189,15 @@ void JitArm::bcx(UGeckoInstruction inst)
else
pConditionDontBranch = B_CC(CC_NEQ); // Not Zero
}
gpr.Unlock(rA, rB);
if (inst.LK)
ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4); // Careful, destroys R14, R12

{
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rB, Jumpto);
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
//ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4); // Careful, destroys R14, R12
}
gpr.Unlock(rA, rB);

u32 destination;
if(inst.AA)
destination = SignExt16(inst.BD << 2);
Expand Down Expand Up @@ -222,13 +228,18 @@ void JitArm::bcctrx(UGeckoInstruction inst)
// BO_2 == 1z1zz -> b always

//NPC = CTR & 0xfffffffc;
if(inst.LK_3)
ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
MOVI2R(rA, (u32)&CTR);

if(inst.LK_3)
{
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rA, Jumpto);
STR(R9, rA, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
// ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
}
MVN(rB, 0x3); // 0xFFFFFFFC
LDR(rA, rA);
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));
AND(rA, rA, rB);
gpr.Unlock(rB);
WriteExitDestInR(rA);
Expand All @@ -242,7 +253,7 @@ void JitArm::bcctrx(UGeckoInstruction inst)
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();

LDRB(rA, R9, STRUCT_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
LDRB(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
TST(rA, 8 >> (inst.BI & 3));
CCFlags branch;
if (inst.BO_2 & BO_BRANCH_IF_TRUE)
Expand All @@ -251,17 +262,14 @@ void JitArm::bcctrx(UGeckoInstruction inst)
branch = CC_NEQ;
FixupBranch b = B_CC(branch);

MOVI2R(rA, (u32)&CTR);
LDR(rA, rA);
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));
MVN(rB, 0x3); // 0xFFFFFFFC
AND(rA, rA, rB);

if (inst.LK_3){
ARMReg rC = gpr.GetReg(false);
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rB, (u32)&LR);
MOVI2R(rC, Jumpto);
STR(rB, rC);
MOVI2R(rB, Jumpto);
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
//ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
}
gpr.Unlock(rB); // rA gets unlocked in WriteExitDestInR
Expand All @@ -279,7 +287,11 @@ void JitArm::bclrx(UGeckoInstruction inst)
(inst.BO & (1 << 4)) && (inst.BO & (1 << 2))) {
if (inst.LK)
{
ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
ARMReg rA = gpr.GetReg(false);
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rA, Jumpto);
STR(R9, rA, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
// ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
}
return;
}
Expand All @@ -291,10 +303,9 @@ void JitArm::bclrx(UGeckoInstruction inst)
FixupBranch pCTRDontBranch;
if ((inst.BO & BO_DONT_DECREMENT_FLAG) == 0) // Decrement and test CTR
{
MOVI2R(rA, (u32)&CTR);
LDR(rB, rA);
LDR(rB, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));
SUBS(rB, rB, 1);
STR(rA, rB);
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_CTR]));

//SUB(32, M(&CTR), Imm8(1));
if (inst.BO & BO_BRANCH_IF_CTR_0)
Expand All @@ -306,7 +317,7 @@ void JitArm::bclrx(UGeckoInstruction inst)
FixupBranch pConditionDontBranch;
if ((inst.BO & BO_DONT_CHECK_CONDITION) == 0) // Test a CR bit
{
LDRB(rA, R9, STRUCT_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
LDRB(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + (inst.BI >> 2));
TST(rA, 8 >> (inst.BI & 3));
//TEST(8, M(&PowerPC::ppcState.cr_fast[inst.BI >> 2]), Imm8(8 >> (inst.BI & 3)));
if (inst.BO & BO_BRANCH_IF_TRUE) // Conditional branch
Expand All @@ -324,16 +335,13 @@ void JitArm::bclrx(UGeckoInstruction inst)

//MOV(32, R(EAX), M(&LR));
//AND(32, R(EAX), Imm32(0xFFFFFFFC));
MOVI2R(rA, (u32)&LR);
MVN(rB, 0x3); // 0xFFFFFFFC
LDR(rA, rA);
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
AND(rA, rA, rB);
if (inst.LK){
ARMReg rC = gpr.GetReg(false);
u32 Jumpto = js.compilerPC + 4;
MOVI2R(rB, (u32)&LR);
MOVI2R(rC, Jumpto);
STR(rB, rC);
MOVI2R(rB, Jumpto);
STR(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, spr[SPR_LR]));
//ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
}
gpr.Unlock(rB); // rA gets unlocked in WriteExitDestInR
Expand Down
6 changes: 3 additions & 3 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
View file
Expand Up @@ -40,7 +40,7 @@ void JitArm::GenerateRC(int cr) {
SetCC(CC_MI); MOV(rB, 0x8); // Result < 0
SetCC();

STRB(R9, rB, STRUCT_OFF(PowerPC::ppcState, cr_fast) + cr);
STRB(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + cr);
gpr.Unlock(rB);
}
void JitArm::ComputeRC(int cr) {
Expand All @@ -51,7 +51,7 @@ void JitArm::ComputeRC(int cr) {
SetCC(CC_GT); MOV(rB, 0x4); // Result > 0
SetCC();

STRB(R9, rB, STRUCT_OFF(PowerPC::ppcState, cr_fast) + cr);
STRB(R9, rB, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + cr);
gpr.Unlock(rB);
}

Expand Down Expand Up @@ -232,7 +232,7 @@ void JitArm::cmpli(UGeckoInstruction inst)
SetCC(CC_HI); MOV(rA, 0x4); // Result > 0
SetCC();

STRB(R9, rA, STRUCT_OFF(PowerPC::ppcState, cr_fast) + crf);
STRB(R9, rA, PPCSTATE_OFF(PowerPC::ppcState, cr_fast) + crf);
gpr.Unlock(rA);

}
Expand Down
10 changes: 5 additions & 5 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
View file
Expand Up @@ -100,7 +100,7 @@ void JitArm::stwu(UGeckoInstruction inst)

// Check and set the update before writing since calling a function can
// mess with the "special registers R11+ which may cause some issues.
LDR(Function, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(Function, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(Function, EXCEPTION_DSI);
FixupBranch DoNotWrite = B_CC(CC_EQ);
MOV(RA, Addr);
Expand Down Expand Up @@ -198,7 +198,7 @@ void JitArm::lbz(UGeckoInstruction inst)
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
ARMReg RD = gpr.R(inst.RD);
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);
#if FASTMEM
Expand Down Expand Up @@ -245,7 +245,7 @@ void JitArm::lhz(UGeckoInstruction inst)
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
ARMReg RD = gpr.R(inst.RD);
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);
#if 0 // FASTMEM
Expand Down Expand Up @@ -295,7 +295,7 @@ void JitArm::lwz(UGeckoInstruction inst)
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
ARMReg RD = gpr.R(inst.RD);
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);

Expand Down Expand Up @@ -369,7 +369,7 @@ void JitArm::lwzx(UGeckoInstruction inst)

ARMReg RB = gpr.R(inst.RB);
ARMReg RD = gpr.R(inst.RD);
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);
#if FASTMEM
Expand Down
2 changes: 1 addition & 1 deletion Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
View file
Expand Up @@ -40,7 +40,7 @@ void JitArm::lfs(UGeckoInstruction inst)

ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
LDR(rA, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(rA, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);

Expand Down
13 changes: 3 additions & 10 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
View file
Expand Up @@ -70,9 +70,7 @@ void JitArm::mtspr(UGeckoInstruction inst)
}

// OK, this is easy.
ARMReg rA = gpr.GetReg(false);
MOVI2R(rA, (u32)&PowerPC::ppcState.spr);
STR(rA, RD, iIndex * 4);
STR(R9, RD, PPCSTATE_OFF(PowerPC::ppcState, spr) + iIndex * 4);
}

void JitArm::mfspr(UGeckoInstruction inst)
Expand All @@ -91,9 +89,7 @@ void JitArm::mfspr(UGeckoInstruction inst)
Default(inst);
return;
default:
ARMReg rA = gpr.GetReg(false);
MOVI2R(rA, (u32)&PowerPC::ppcState.spr);
LDR(RD, rA, iIndex * 4);
LDR(RD, R9, PPCSTATE_OFF(PowerPC::ppcState, spr) + iIndex * 4);
break;
}
}
Expand All @@ -103,9 +99,6 @@ void JitArm::mtmsr(UGeckoInstruction inst)
// Don't interpret this, if we do we get thrown out
//JITDISABLE(SystemRegisters)

ARMReg rA = gpr.GetReg();
MOVI2R(rA, (u32)&MSR);
STR(rA, gpr.R(inst.RS));
gpr.Unlock(rA);
STR(R9, gpr.R(inst.RS), PPCSTATE_OFF(PowerPC::ppcState, msr));
WriteExit(js.compilerPC + 4, 0);
}
22 changes: 11 additions & 11 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitAsm.cpp
View file
Expand Up @@ -47,7 +47,7 @@ void JitArmAsmRoutineManager::Generate()
PUSH(2, R11, _LR); // R11 is frame pointer in Debug.

MOVI2R(R0, (u32)&CoreTiming::downcount);
MOVI2R(R9, (u32)&PowerPC::ppcState);
MOVI2R(R9, (u32)&PowerPC::ppcState.spr[0]);

FixupBranch skipToRealDispatcher = B();
dispatcher = GetCodePtr();
Expand All @@ -63,7 +63,7 @@ void JitArmAsmRoutineManager::Generate()

// This block of code gets the address of the compiled block of code
// It runs though to the compiling portion if it isn't found
LDR(R12, R9, STRUCT_OFF(PowerPC::ppcState, pc));// Load the current PC into R12
LDR(R12, R9, PPCSTATE_OFF(PowerPC::ppcState, pc));// Load the current PC into R12

MOVI2R(R14, JIT_ICACHE_MASK); // Potential for optimization
AND(R12, R12, R14); // R12 contains PC & JIT_ICACHE_MASK here.
Expand Down Expand Up @@ -92,20 +92,20 @@ void JitArmAsmRoutineManager::Generate()
// If we get to this point, that means that we don't have the block cached to execute
// So call ArmJit to compile the block and then execute it.
MOVI2R(R14, (u32)&Jit);
LDR(R0, R9, STRUCT_OFF(PowerPC::ppcState, pc));
LDR(R0, R9, PPCSTATE_OFF(PowerPC::ppcState, pc));
BL(R14);

B(dispatcherNoCheck);

// fpException()
// Floating Point Exception Check, Jumped to if false
fpException = GetCodePtr();
LDR(R0, R9, STRUCT_OFF(PowerPC::ppcState, Exceptions));
LDR(R0, R9, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
ORR(R0, R0, EXCEPTION_FPU_UNAVAILABLE);
STR(R9, R0, STRUCT_OFF(PowerPC::ppcState, Exceptions));
STR(R9, R0, PPCSTATE_OFF(PowerPC::ppcState, Exceptions));
QuickCallFunction(R14, (void*)&PowerPC::CheckExceptions);
LDR(R0, R9, STRUCT_OFF(PowerPC::ppcState, npc));
STR(R9, R0, STRUCT_OFF(PowerPC::ppcState, pc));
LDR(R0, R9, PPCSTATE_OFF(PowerPC::ppcState, npc));
STR(R9, R0, PPCSTATE_OFF(PowerPC::ppcState, pc));
B(dispatcher);

SetJumpTarget(bail);
Expand All @@ -116,11 +116,11 @@ void JitArmAsmRoutineManager::Generate()

// Does exception checking
testExceptions = GetCodePtr();
LDR(R0, R9, STRUCT_OFF(PowerPC::ppcState, pc));
STR(R9, R0, STRUCT_OFF(PowerPC::ppcState, npc));
LDR(R0, R9, PPCSTATE_OFF(PowerPC::ppcState, pc));
STR(R9, R0, PPCSTATE_OFF(PowerPC::ppcState, npc));
QuickCallFunction(R14, (void*)&PowerPC::CheckExceptions);
LDR(R0, R9, STRUCT_OFF(PowerPC::ppcState, npc));
STR(R9, R0, STRUCT_OFF(PowerPC::ppcState, pc));
LDR(R0, R9, PPCSTATE_OFF(PowerPC::ppcState, npc));
STR(R9, R0, PPCSTATE_OFF(PowerPC::ppcState, pc));
// Check the state pointer to see if we are exiting
// Gets checked on every exception check
MOVI2R(R0, (u32)PowerPC::GetStatePtr());
Expand Down
9 changes: 5 additions & 4 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.cpp
View file
Expand Up @@ -15,6 +15,7 @@
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/

#include "Jit.h"
#include "JitFPRCache.h"

ArmFPRCache::ArmFPRCache()
Expand Down Expand Up @@ -122,7 +123,7 @@ ARMReg ArmFPRCache::GetPPCReg(u32 preg, bool PS1, bool preLoad)
for (u8 a = 0; a < NUMPPCREG; ++a)
if (ArmCRegs[a].PPCReg == 33)
{
u16 offset = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
u16 offset = PPCSTATE_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
if (preLoad)
emit->VLDR(ArmCRegs[a].Reg, R9, offset);
ArmCRegs[a].PPCReg = preg;
Expand All @@ -131,10 +132,10 @@ ARMReg ArmFPRCache::GetPPCReg(u32 preg, bool PS1, bool preLoad)
return ArmCRegs[a].Reg;
}
// Alright, we couldn't get a free space, dump that least used register
u16 offsetOld = STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[Num].PPCReg * 16) + (ArmCRegs[Num].PS1 ? 8 : 0);
u16 offsetOld = PPCSTATE_OFF(PowerPC::ppcState, ps) + (ArmCRegs[Num].PPCReg * 16) + (ArmCRegs[Num].PS1 ? 8 : 0);
emit->VSTR(ArmCRegs[Num].Reg, R9, offsetOld);

u16 offsetNew = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
u16 offsetNew = PPCSTATE_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
if (preLoad)
emit->VLDR(ArmCRegs[Num].Reg, R9, offsetNew);
ArmCRegs[Num].PPCReg = preg;
Expand All @@ -159,7 +160,7 @@ void ArmFPRCache::Flush()
for(u8 a = 0; a < NUMPPCREG; ++a)
if (ArmCRegs[a].PPCReg != 33)
{
u16 offset = STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[a].PPCReg * 16) + (ArmCRegs[a].PS1 ? 8 : 0);
u16 offset = PPCSTATE_OFF(PowerPC::ppcState, ps) + (ArmCRegs[a].PPCReg * 16) + (ArmCRegs[a].PS1 ? 8 : 0);
emit->VSTR(ArmCRegs[a].Reg, R9, offset);
ArmCRegs[a].PPCReg = 33;
ArmCRegs[a].LastLoad = 0;
Expand Down
9 changes: 5 additions & 4 deletions Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp
View file
Expand Up @@ -15,6 +15,7 @@
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/

#include "Jit.h"
#include "JitRegCache.h"

ArmRegCache::ArmRegCache()
Expand Down Expand Up @@ -141,14 +142,14 @@ ARMReg ArmRegCache::R(u32 preg)
for (u8 a = 0; a < NUMPPCREG; ++a)
if (ArmCRegs[a].PPCReg == 33)
{
emit->LDR(ArmCRegs[a].Reg, R9, STRUCT_OFF(PowerPC::ppcState, gpr) + preg * 4);
emit->LDR(ArmCRegs[a].Reg, R9, PPCSTATE_OFF(PowerPC::ppcState, gpr) + preg * 4);
ArmCRegs[a].PPCReg = preg;
ArmCRegs[a].LastLoad = 0;
return ArmCRegs[a].Reg;
}
// Alright, we couldn't get a free space, dump that least used register
emit->STR(R9, ArmCRegs[Num].Reg, STRUCT_OFF(PowerPC::ppcState, gpr) + ArmCRegs[Num].PPCReg * 4);
emit->LDR(ArmCRegs[Num].Reg, R9, STRUCT_OFF(PowerPC::ppcState, gpr) + preg * 4);
emit->STR(R9, ArmCRegs[Num].Reg, PPCSTATE_OFF(PowerPC::ppcState, gpr) + ArmCRegs[Num].PPCReg * 4);
emit->LDR(ArmCRegs[Num].Reg, R9, PPCSTATE_OFF(PowerPC::ppcState, gpr) + preg * 4);
ArmCRegs[Num].PPCReg = preg;
ArmCRegs[Num].LastLoad = 0;
return ArmCRegs[Num].Reg;
Expand All @@ -159,7 +160,7 @@ void ArmRegCache::Flush()
for(u8 a = 0; a < NUMPPCREG; ++a)
if (ArmCRegs[a].PPCReg != 33)
{
emit->STR(R9, ArmCRegs[a].Reg, STRUCT_OFF(PowerPC::ppcState, gpr) + ArmCRegs[a].PPCReg * 4);
emit->STR(R9, ArmCRegs[a].Reg, PPCSTATE_OFF(PowerPC::ppcState, gpr) + ArmCRegs[a].PPCReg * 4);
ArmCRegs[a].PPCReg = 33;
ArmCRegs[a].LastLoad = 0;
}
Expand Down