70 Source/Core/Core/HW/MMIO.cpp
View file
@@ -112,12 +112,12 @@ template <typename T>
class ComplexHandlingMethod : public ReadHandlingMethod<T>, public WriteHandlingMethod<T>
{
public:
explicit ComplexHandlingMethod(std::function<T(u32)> read_lambda)
explicit ComplexHandlingMethod(std::function<T(Core::System&, u32)> read_lambda)
: read_lambda_(read_lambda), write_lambda_(InvalidWriteLambda())
{
}

explicit ComplexHandlingMethod(std::function<void(u32, T)> write_lambda)
explicit ComplexHandlingMethod(std::function<void(Core::System&, u32, T)> write_lambda)
: read_lambda_(InvalidReadLambda()), write_lambda_(write_lambda)
{
}
@@ -134,35 +134,35 @@ class ComplexHandlingMethod : public ReadHandlingMethod<T>, public WriteHandling
}

private:
std::function<T(u32)> InvalidReadLambda() const
std::function<T(Core::System&, u32)> InvalidReadLambda() const
{
return [](u32) {
return [](Core::System&, u32) {
DEBUG_ASSERT_MSG(MEMMAP, 0,
"Called the read lambda on a write "
"complex handler.");
return 0;
};
}

std::function<void(u32, T)> InvalidWriteLambda() const
std::function<void(Core::System&, u32, T)> InvalidWriteLambda() const
{
return [](u32, T) {
return [](Core::System&, u32, T) {
DEBUG_ASSERT_MSG(MEMMAP, 0,
"Called the write lambda on a read "
"complex handler.");
};
}

std::function<T(u32)> read_lambda_;
std::function<void(u32, T)> write_lambda_;
std::function<T(Core::System&, u32)> read_lambda_;
std::function<void(Core::System&, u32, T)> write_lambda_;
};
template <typename T>
ReadHandlingMethod<T>* ComplexRead(std::function<T(u32)> lambda)
ReadHandlingMethod<T>* ComplexRead(std::function<T(Core::System&, u32)> lambda)
{
return new ComplexHandlingMethod<T>(lambda);
}
template <typename T>
WriteHandlingMethod<T>* ComplexWrite(std::function<void(u32, T)> lambda)
WriteHandlingMethod<T>* ComplexWrite(std::function<void(Core::System&, u32, T)> lambda)
{
return new ComplexHandlingMethod<T>(lambda);
}
@@ -172,7 +172,7 @@ WriteHandlingMethod<T>* ComplexWrite(std::function<void(u32, T)> lambda)
template <typename T>
ReadHandlingMethod<T>* InvalidRead()
{
return ComplexRead<T>([](u32 addr) {
return ComplexRead<T>([](Core::System&, u32 addr) {
ERROR_LOG_FMT(MEMMAP, "Trying to read {} bits from an invalid MMIO (addr={:08x})",
8 * sizeof(T), addr);
return -1;
@@ -181,7 +181,7 @@ ReadHandlingMethod<T>* InvalidRead()
template <typename T>
WriteHandlingMethod<T>* InvalidWrite()
{
return ComplexWrite<T>([](u32 addr, T val) {
return ComplexWrite<T>([](Core::System&, u32 addr, T val) {
ERROR_LOG_FMT(MEMMAP, "Trying to write {} bits to an invalid MMIO (addr={:08x}, val={:08x})",
8 * sizeof(T), addr, val);
});
@@ -229,8 +229,9 @@ ReadHandlingMethod<T>* ReadToSmaller(Mapping* mmio, u32 high_part_addr, u32 low_
ReadHandler<ST>* low_part = &mmio->GetHandlerForRead<ST>(low_part_addr);

// TODO(delroth): optimize
return ComplexRead<T>([=](u32 addr) {
return ((T)high_part->Read(high_part_addr) << (8 * sizeof(ST))) | low_part->Read(low_part_addr);
return ComplexRead<T>([=](Core::System& system, u32 addr) {
return ((T)high_part->Read(system, high_part_addr) << (8 * sizeof(ST))) |
low_part->Read(system, low_part_addr);
});
}

@@ -243,9 +244,9 @@ WriteHandlingMethod<T>* WriteToSmaller(Mapping* mmio, u32 high_part_addr, u32 lo
WriteHandler<ST>* low_part = &mmio->GetHandlerForWrite<ST>(low_part_addr);

// TODO(delroth): optimize
return ComplexWrite<T>([=](u32 addr, T val) {
high_part->Write(high_part_addr, val >> (8 * sizeof(ST)));
low_part->Write(low_part_addr, (ST)val);
return ComplexWrite<T>([=](Core::System& system, u32 addr, T val) {
high_part->Write(system, high_part_addr, val >> (8 * sizeof(ST)));
low_part->Write(system, low_part_addr, (ST)val);
});
}

@@ -257,8 +258,9 @@ ReadHandlingMethod<T>* ReadToLarger(Mapping* mmio, u32 larger_addr, u32 shift)
ReadHandler<LT>* large = &mmio->GetHandlerForRead<LT>(larger_addr);

// TODO(delroth): optimize
return ComplexRead<T>(
[large, shift](u32 addr) { return large->Read(addr & ~(sizeof(LT) - 1)) >> shift; });
return ComplexRead<T>([large, shift](Core::System& system, u32 addr) {
return large->Read(system, addr & ~(sizeof(LT) - 1)) >> shift;
});
}

// Inplementation of the ReadHandler and WriteHandler class. There is a lot of
@@ -290,15 +292,15 @@ void ReadHandler<T>::Visit(ReadHandlingMethodVisitor<T>& visitor)
}

template <typename T>
T ReadHandler<T>::Read(u32 addr)
T ReadHandler<T>::Read(Core::System& system, u32 addr)
{
// Check if the handler has already been initialized. For real
// handlers, this will always be the case, so this branch should be
// easily predictable.
if (!m_Method)
InitializeInvalid();

return m_ReadFunc(addr);
return m_ReadFunc(system, addr);
}

template <typename T>
@@ -310,19 +312,22 @@ void ReadHandler<T>::ResetMethod(ReadHandlingMethod<T>* method)
{
virtual ~FuncCreatorVisitor() = default;

std::function<T(u32)> ret;
std::function<T(Core::System&, u32)> ret;

void VisitConstant(T value) override
{
ret = [value](u32) { return value; };
ret = [value](Core::System&, u32) { return value; };
}

void VisitDirect(const T* addr, u32 mask) override
{
ret = [addr, mask](u32) { return *addr & mask; };
ret = [addr, mask](Core::System&, u32) { return *addr & mask; };
}

void VisitComplex(const std::function<T(u32)>* lambda) override { ret = *lambda; }
void VisitComplex(const std::function<T(Core::System&, u32)>* lambda) override
{
ret = *lambda;
}
};

FuncCreatorVisitor v;
@@ -362,15 +367,15 @@ void WriteHandler<T>::Visit(WriteHandlingMethodVisitor<T>& visitor)
}

template <typename T>
void WriteHandler<T>::Write(u32 addr, T val)
void WriteHandler<T>::Write(Core::System& system, u32 addr, T val)
{
// Check if the handler has already been initialized. For real
// handlers, this will always be the case, so this branch should be
// easily predictable.
if (!m_Method)
InitializeInvalid();

m_WriteFunc(addr, val);
m_WriteFunc(system, addr, val);
}

template <typename T>
@@ -382,19 +387,22 @@ void WriteHandler<T>::ResetMethod(WriteHandlingMethod<T>* method)
{
virtual ~FuncCreatorVisitor() = default;

std::function<void(u32, T)> ret;
std::function<void(Core::System&, u32, T)> ret;

void VisitNop() override
{
ret = [](u32, T) {};
ret = [](Core::System&, u32, T) {};
}

void VisitDirect(T* ptr, u32 mask) override
{
ret = [ptr, mask](u32, T val) { *ptr = val & mask; };
ret = [ptr, mask](Core::System&, u32, T val) { *ptr = val & mask; };
}

void VisitComplex(const std::function<void(u32, T)>* lambda) override { ret = *lambda; }
void VisitComplex(const std::function<void(Core::System&, u32, T)>* lambda) override
{
ret = *lambda;
}
};

FuncCreatorVisitor v;
5 Source/Core/Core/HW/MMIO.h
View file
@@ -15,6 +15,7 @@
#include "Core/ConfigManager.h"
#include "Core/HW/GPFifo.h"
#include "Core/HW/MMIOHandlers.h"
#include "Core/System.h"

namespace MMIO
{
@@ -132,13 +133,13 @@ class Mapping
template <typename Unit>
Unit Read(u32 addr)
{
return GetHandlerForRead<Unit>(addr).Read(addr);
return GetHandlerForRead<Unit>(addr).Read(Core::System::GetInstance(), addr);
}

template <typename Unit>
void Write(u32 addr, Unit val)
{
GetHandlerForWrite<Unit>(addr).Write(addr, val);
GetHandlerForWrite<Unit>(addr).Write(Core::System::GetInstance(), addr, val);
}

// Handlers access interface.
26 Source/Core/Core/HW/MMIOHandlers.h
View file
@@ -18,6 +18,10 @@
// u8/u16/u32 with the same code while providing type safety: it is impossible
// to mix code from these types, and the type system enforces it.

namespace Core
{
class System;
}
namespace MMIO
{
class Mapping;
@@ -51,9 +55,9 @@ WriteHandlingMethod<T>* DirectWrite(T* addr, u32 mask = 0xFFFFFFFF);
// to directly provide a function that will be called when a read/write needs
// to be done.
template <typename T>
ReadHandlingMethod<T>* ComplexRead(std::function<T(u32)>);
ReadHandlingMethod<T>* ComplexRead(std::function<T(Core::System&, u32)>);
template <typename T>
WriteHandlingMethod<T>* ComplexWrite(std::function<void(u32, T)>);
WriteHandlingMethod<T>* ComplexWrite(std::function<void(Core::System&, u32, T)>);

// Invalid: log an error and return -1 in case of a read. These are the default
// handlers set for all MMIO types.
@@ -97,15 +101,15 @@ class ReadHandlingMethodVisitor
public:
virtual void VisitConstant(T value) = 0;
virtual void VisitDirect(const T* addr, u32 mask) = 0;
virtual void VisitComplex(const std::function<T(u32)>* lambda) = 0;
virtual void VisitComplex(const std::function<T(Core::System&, u32)>* lambda) = 0;
};
template <typename T>
class WriteHandlingMethodVisitor
{
public:
virtual void VisitNop() = 0;
virtual void VisitDirect(T* addr, u32 mask) = 0;
virtual void VisitComplex(const std::function<void(u32, T)>* lambda) = 0;
virtual void VisitComplex(const std::function<void(Core::System&, u32, T)>* lambda) = 0;
};

// These classes are INTERNAL. Do not use outside of the MMIO implementation
@@ -126,7 +130,7 @@ class ReadHandler
// Entry point for read handling method visitors.
void Visit(ReadHandlingMethodVisitor<T>& visitor);

T Read(u32 addr);
T Read(Core::System& system, u32 addr);

// Internal method called when changing the internal method object. Its
// main role is to make sure the read function is updated at the same time.
@@ -137,7 +141,7 @@ class ReadHandler
// useless initialization of thousands of unused handler objects.
void InitializeInvalid();
std::unique_ptr<ReadHandlingMethod<T>> m_Method;
std::function<T(u32)> m_ReadFunc;
std::function<T(Core::System&, u32)> m_ReadFunc;
};
template <typename T>
class WriteHandler
@@ -153,7 +157,7 @@ class WriteHandler
// Entry point for write handling method visitors.
void Visit(WriteHandlingMethodVisitor<T>& visitor);

void Write(u32 addr, T val);
void Write(Core::System& system, u32 addr, T val);

// Internal method called when changing the internal method object. Its
// main role is to make sure the write function is updated at the same
@@ -165,7 +169,7 @@ class WriteHandler
// useless initialization of thousands of unused handler objects.
void InitializeInvalid();
std::unique_ptr<WriteHandlingMethod<T>> m_Method;
std::function<void(u32, T)> m_WriteFunc;
std::function<void(Core::System&, u32, T)> m_WriteFunc;
};

// Boilerplate boilerplate boilerplate.
@@ -182,8 +186,10 @@ class WriteHandler
MaybeExtern template WriteHandlingMethod<T>* Nop<T>(); \
MaybeExtern template ReadHandlingMethod<T>* DirectRead(const T* addr, u32 mask); \
MaybeExtern template WriteHandlingMethod<T>* DirectWrite(T* addr, u32 mask); \
MaybeExtern template ReadHandlingMethod<T>* ComplexRead<T>(std::function<T(u32)>); \
MaybeExtern template WriteHandlingMethod<T>* ComplexWrite<T>(std::function<void(u32, T)>); \
MaybeExtern template ReadHandlingMethod<T>* ComplexRead<T>( \
std::function<T(Core::System&, u32)>); \
MaybeExtern template WriteHandlingMethod<T>* ComplexWrite<T>( \
std::function<void(Core::System&, u32, T)>); \
MaybeExtern template ReadHandlingMethod<T>* InvalidRead<T>(); \
MaybeExtern template WriteHandlingMethod<T>* InvalidWrite<T>(); \
MaybeExtern template class ReadHandler<T>; \
10 Source/Core/Core/HW/ProcessorInterface.cpp
View file
@@ -82,13 +82,13 @@ void Init()
void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
mmio->Register(base | PI_INTERRUPT_CAUSE, MMIO::DirectRead<u32>(&m_InterruptCause),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
m_InterruptCause &= ~val;
UpdateException();
}));

mmio->Register(base | PI_INTERRUPT_MASK, MMIO::DirectRead<u32>(&m_InterruptMask),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
m_InterruptMask = val;
UpdateException();
}));
@@ -103,7 +103,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
MMIO::DirectWrite<u32>(&Fifo_CPUWritePointer, 0xFFFFFFE0));

mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead<u32>(),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
// Used by GXAbortFrame
INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_FIFO_RESET: {:08x}", val);
if ((val & 1) != 0)
@@ -125,11 +125,11 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
}
}));

mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](u32) {
mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](Core::System&, u32) {
DEBUG_LOG_FMT(PROCESSORINTERFACE, "Read PI_RESET_CODE: {:08x}", m_ResetCode);
return m_ResetCode;
}),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
m_ResetCode = val;
INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_RESET_CODE: {:08x}", m_ResetCode);
if (!SConfig::GetInstance().bWii && ~m_ResetCode & 0x4)
31 Source/Core/Core/HW/SI/SI.cpp
View file
@@ -490,14 +490,14 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
const u32 address = base | static_cast<u32>(io_buffer_base + i);

mmio->Register(address, MMIO::ComplexRead<u32>([i](u32) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
mmio->Register(address, MMIO::ComplexRead<u32>([i](Core::System& system, u32) {
auto& state = system.GetSerialInterfaceState().GetData();
u32 val;
std::memcpy(&val, &state.si_buffer[i], sizeof(val));
return Common::swap32(val);
}),
MMIO::ComplexWrite<u32>([i](u32, u32 val) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
MMIO::ComplexWrite<u32>([i](Core::System& system, u32, u32 val) {
auto& state = system.GetSerialInterfaceState().GetData();
val = Common::swap32(val);
std::memcpy(&state.si_buffer[i], &val, sizeof(val));
}));
@@ -506,14 +506,14 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
const u32 address = base | static_cast<u32>(io_buffer_base + i);

mmio->Register(address, MMIO::ComplexRead<u16>([i](u32) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
mmio->Register(address, MMIO::ComplexRead<u16>([i](Core::System& system, u32) {
auto& state = system.GetSerialInterfaceState().GetData();
u16 val;
std::memcpy(&val, &state.si_buffer[i], sizeof(val));
return Common::swap16(val);
}),
MMIO::ComplexWrite<u16>([i](u32, u16 val) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
MMIO::ComplexWrite<u16>([i](Core::System& system, u32, u16 val) {
auto& state = system.GetSerialInterfaceState().GetData();
val = Common::swap16(val);
std::memcpy(&state.si_buffer[i], &val, sizeof(val));
}));
@@ -533,16 +533,16 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
MMIO::DirectRead<u32>(&state.channel[i].out.hex),
MMIO::DirectWrite<u32>(&state.channel[i].out.hex));
mmio->Register(base | (SI_CHANNEL_0_IN_HI + 0xC * i),
MMIO::ComplexRead<u32>([i, rdst_bit](u32) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
MMIO::ComplexRead<u32>([i, rdst_bit](Core::System& system, u32) {
auto& state = system.GetSerialInterfaceState().GetData();
state.status_reg.hex &= ~(1U << rdst_bit);
UpdateInterrupts();
return state.channel[i].in_hi.hex;
}),
MMIO::DirectWrite<u32>(&state.channel[i].in_hi.hex));
mmio->Register(base | (SI_CHANNEL_0_IN_LO + 0xC * i),
MMIO::ComplexRead<u32>([i, rdst_bit](u32) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
MMIO::ComplexRead<u32>([i, rdst_bit](Core::System& system, u32) {
auto& state = system.GetSerialInterfaceState().GetData();
state.status_reg.hex &= ~(1U << rdst_bit);
UpdateInterrupts();
return state.channel[i].in_lo.hex;
@@ -554,8 +554,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
MMIO::DirectWrite<u32>(&state.poll.hex));

mmio->Register(base | SI_COM_CSR, MMIO::DirectRead<u32>(&state.com_csr.hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
auto& system = Core::System::GetInstance();
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
auto& state = system.GetSerialInterfaceState().GetData();
const USIComCSR tmp_com_csr(val);

@@ -584,8 +583,8 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
}));

mmio->Register(base | SI_STATUS_REG, MMIO::DirectRead<u32>(&state.status_reg.hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
auto& state = Core::System::GetInstance().GetSerialInterfaceState().GetData();
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
auto& state = system.GetSerialInterfaceState().GetData();
const USIStatusReg tmp_status(val);

// clear bits ( if (tmp.bit) SISR.bit=0 )
66 Source/Core/Core/HW/VideoInterface.cpp
View file
@@ -266,62 +266,62 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
for (auto& mapped_var : update_params_on_read_vars)
{
mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
MMIO::ComplexWrite<u16>([mapped_var](u32, u16 val) {
MMIO::ComplexWrite<u16>([mapped_var](Core::System&, u32, u16 val) {
*mapped_var.ptr = val;
UpdateParameters();
}));
}

// XFB related MMIOs that require special handling on writes.
mmio->Register(base | VI_FB_LEFT_TOP_HI, MMIO::DirectRead<u16>(&state.xfb_info_top.Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.xfb_info_top.Hi = val;
if (state.xfb_info_top.CLRPOFF)
state.xfb_info_top.POFF = 0;
}));
mmio->Register(base | VI_FB_LEFT_BOTTOM_HI, MMIO::DirectRead<u16>(&state.xfb_info_bottom.Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.xfb_info_bottom.Hi = val;
if (state.xfb_info_bottom.CLRPOFF)
state.xfb_info_bottom.POFF = 0;
}));
mmio->Register(base | VI_FB_RIGHT_TOP_HI, MMIO::DirectRead<u16>(&state.xfb_3d_info_top.Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.xfb_3d_info_top.Hi = val;
if (state.xfb_3d_info_top.CLRPOFF)
state.xfb_3d_info_top.POFF = 0;
}));
mmio->Register(base | VI_FB_RIGHT_BOTTOM_HI, MMIO::DirectRead<u16>(&state.xfb_3d_info_bottom.Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.xfb_3d_info_bottom.Hi = val;
if (state.xfb_3d_info_bottom.CLRPOFF)
state.xfb_3d_info_bottom.POFF = 0;
}));

// MMIOs with unimplemented writes that trigger warnings.
mmio->Register(
base | VI_VERTICAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](u32) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
base | VI_VERTICAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
auto& state = system.GetVideoInterfaceState().GetData();
return 1 + (state.half_line_count) / 2;
}),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
WARN_LOG_FMT(
VIDEOINTERFACE,
"Changing vertical beam position to {:#06x} - not documented or implemented yet", val);
}));
mmio->Register(
base | VI_HORIZONTAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](u32) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
base | VI_HORIZONTAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
auto& state = system.GetVideoInterfaceState().GetData();
u16 value = static_cast<u16>(
1 + state.h_timing_0.HLW * (CoreTiming::GetTicks() - state.ticks_last_line_start) /
(GetTicksPerHalfLine()));
return std::clamp<u16>(value, 1, state.h_timing_0.HLW * 2);
}),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
WARN_LOG_FMT(
VIDEOINTERFACE,
"Changing horizontal beam position to {:#06x} - not documented or implemented yet",
@@ -331,50 +331,50 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// The following MMIOs are interrupts related and update interrupt status
// on writes.
mmio->Register(base | VI_PRERETRACE_HI, MMIO::DirectRead<u16>(&state.interrupt_register[0].Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.interrupt_register[0].Hi = val;
UpdateInterrupts();
}));
mmio->Register(base | VI_POSTRETRACE_HI, MMIO::DirectRead<u16>(&state.interrupt_register[1].Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.interrupt_register[1].Hi = val;
UpdateInterrupts();
}));
mmio->Register(base | VI_DISPLAY_INTERRUPT_2_HI,
MMIO::DirectRead<u16>(&state.interrupt_register[2].Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.interrupt_register[2].Hi = val;
UpdateInterrupts();
}));
mmio->Register(base | VI_DISPLAY_INTERRUPT_3_HI,
MMIO::DirectRead<u16>(&state.interrupt_register[3].Hi),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.interrupt_register[3].Hi = val;
UpdateInterrupts();
}));

// Unknown anti-aliasing related MMIO register: puts a warning on log and
// needs to shift/mask when reading/writing.
mmio->Register(base | VI_UNK_AA_REG_HI, MMIO::ComplexRead<u16>([](u32) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
mmio->Register(base | VI_UNK_AA_REG_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
auto& state = system.GetVideoInterfaceState().GetData();
return state.unknown_aa_register >> 16;
}),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.unknown_aa_register =
(state.unknown_aa_register & 0x0000FFFF) | ((u32)val << 16);
WARN_LOG_FMT(VIDEOINTERFACE, "Writing to the unknown AA register (hi)");
}));
mmio->Register(base | VI_UNK_AA_REG_LO, MMIO::ComplexRead<u16>([](u32) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
mmio->Register(base | VI_UNK_AA_REG_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
auto& state = system.GetVideoInterfaceState().GetData();
return state.unknown_aa_register & 0xFFFF;
}),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();
state.unknown_aa_register = (state.unknown_aa_register & 0xFFFF0000) | val;
WARN_LOG_FMT(VIDEOINTERFACE, "Writing to the unknown AA register (lo)");
}));
@@ -383,8 +383,8 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// processing needs to be done if a reset is requested.
mmio->Register(base | VI_CONTROL_REGISTER,
MMIO::DirectRead<u16>(&state.display_control_register.Hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
auto& state = Core::System::GetInstance().GetVideoInterfaceState().GetData();
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
auto& state = system.GetVideoInterfaceState().GetData();

UVIDisplayControlRegister tmpConfig(val);
state.display_control_register.ENB = tmpConfig.ENB;
23 Source/Core/Core/HW/WII_IPC.cpp
View file
@@ -174,8 +174,9 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
mmio->Register(base | IPC_PPCMSG, MMIO::InvalidRead<u32>(), MMIO::DirectWrite<u32>(&ppc_msg));

mmio->Register(base | IPC_PPCCTRL, MMIO::ComplexRead<u32>([](u32) { return ctrl.ppc(); }),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
mmio->Register(base | IPC_PPCCTRL,
MMIO::ComplexRead<u32>([](Core::System&, u32) { return ctrl.ppc(); }),
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
ctrl.ppc(val);
// The IPC interrupt is triggered when IY1/IY2 is set and
// Y1/Y2 is written to -- even when this results in clearing the bit.
@@ -190,14 +191,14 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
mmio->Register(base | IPC_ARMMSG, MMIO::DirectRead<u32>(&arm_msg), MMIO::InvalidWrite<u32>());

mmio->Register(base | PPC_IRQFLAG, MMIO::InvalidRead<u32>(),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
ppc_irq_flags &= ~val;
HLE::GetIOS()->UpdateIPC();
CoreTiming::ScheduleEvent(0, updateInterrupts, 0);
}));

mmio->Register(base | PPC_IRQMASK, MMIO::InvalidRead<u32>(),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
ppc_irq_masks = val;
if (ppc_irq_masks & INT_CAUSE_IPC_BROADWAY) // wtf?
Reset();
@@ -206,7 +207,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
}));

mmio->Register(base | GPIOB_OUT, MMIO::DirectRead<u32>(&g_gpio_out.m_hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
g_gpio_out.m_hex =
(val & gpio_owner.m_hex) | (g_gpio_out.m_hex & ~gpio_owner.m_hex);
if (g_gpio_out[GPIO::DO_EJECT])
@@ -218,10 +219,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// TODO: AVE, SLOT_LED
}));
mmio->Register(base | GPIOB_DIR, MMIO::DirectRead<u32>(&gpio_dir.m_hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
gpio_dir.m_hex = (val & gpio_owner.m_hex) | (gpio_dir.m_hex & ~gpio_owner.m_hex);
}));
mmio->Register(base | GPIOB_IN, MMIO::ComplexRead<u32>([](u32) {
mmio->Register(base | GPIOB_IN, MMIO::ComplexRead<u32>([](Core::System&, u32) {
Common::Flags<GPIO> gpio_in;
gpio_in[GPIO::SLOT_IN] = DVDInterface::IsDiscInside();
return gpio_in.m_hex;
@@ -239,7 +240,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// go through the HW_GPIOB registers if the corresponding bit is set in the HW_GPIO_OWNER
// register.
mmio->Register(base | GPIO_OUT, MMIO::DirectRead<u32>(&g_gpio_out.m_hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
g_gpio_out.m_hex =
(g_gpio_out.m_hex & gpio_owner.m_hex) | (val & ~gpio_owner.m_hex);
if (g_gpio_out[GPIO::DO_EJECT])
@@ -251,18 +252,18 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// TODO: AVE, SLOT_LED
}));
mmio->Register(base | GPIO_DIR, MMIO::DirectRead<u32>(&gpio_dir.m_hex),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
gpio_dir.m_hex = (gpio_dir.m_hex & gpio_owner.m_hex) | (val & ~gpio_owner.m_hex);
}));
mmio->Register(base | GPIO_IN, MMIO::ComplexRead<u32>([](u32) {
mmio->Register(base | GPIO_IN, MMIO::ComplexRead<u32>([](Core::System&, u32) {
Common::Flags<GPIO> gpio_in;
gpio_in[GPIO::SLOT_IN] = DVDInterface::IsDiscInside();
return gpio_in.m_hex;
}),
MMIO::Nop<u32>());

mmio->Register(base | HW_RESETS, MMIO::DirectRead<u32>(&resets),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
// A reset occurs when the corresponding bit is cleared
const bool di_reset_triggered = (resets & 0x400) && !(val & 0x400);
resets = val;
7 Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
View file
@@ -19,6 +19,7 @@
#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
#include "Core/PowerPC/MMU.h"
#include "Core/PowerPC/PowerPC.h"
#include "Core/System.h"

using namespace Gen;

@@ -220,7 +221,7 @@ class MMIOReadCodeGenerator : public MMIO::ReadHandlingMethodVisitor<T>
{
LoadAddrMaskToReg(8 * sizeof(T), addr, mask);
}
void VisitComplex(const std::function<T(u32)>* lambda) override
void VisitComplex(const std::function<T(Core::System&, u32)>* lambda) override
{
CallLambda(8 * sizeof(T), lambda);
}
@@ -269,10 +270,10 @@ class MMIOReadCodeGenerator : public MMIO::ReadHandlingMethodVisitor<T>
}
}

void CallLambda(int sbits, const std::function<T(u32)>* lambda)
void CallLambda(int sbits, const std::function<T(Core::System&, u32)>* lambda)
{
m_code->ABI_PushRegistersAndAdjustStack(m_registers_in_use, 0);
m_code->ABI_CallLambdaC(lambda, m_address);
m_code->ABI_CallLambdaPC(lambda, &Core::System::GetInstance(), m_address);
m_code->ABI_PopRegistersAndAdjustStack(m_registers_in_use, 0);
MoveOpArgToReg(sbits, R(ABI_RETURN));
}
20 Source/Core/Core/PowerPC/JitArm64/Jit_Util.cpp
View file
@@ -7,8 +7,8 @@
#include "Common/Common.h"

#include "Core/HW/MMIO.h"

#include "Core/PowerPC/JitArm64/Jit.h"
#include "Core/System.h"

using namespace Arm64Gen;

@@ -28,7 +28,7 @@ class MMIOWriteCodeGenerator : public MMIO::WriteHandlingMethodVisitor<T>
// Do nothing
}
void VisitDirect(T* addr, u32 mask) override { WriteRegToAddr(8 * sizeof(T), addr, mask); }
void VisitComplex(const std::function<void(u32, T)>* lambda) override
void VisitComplex(const std::function<void(Core::System&, u32, T)>* lambda) override
{
CallLambda(8 * sizeof(T), lambda);
}
@@ -72,15 +72,15 @@ class MMIOWriteCodeGenerator : public MMIO::WriteHandlingMethodVisitor<T>
}
}

void CallLambda(int sbits, const std::function<void(u32, T)>* lambda)
void CallLambda(int sbits, const std::function<void(Core::System&, u32, T)>* lambda)
{
ARM64FloatEmitter float_emit(m_emit);

m_emit->ABI_PushRegisters(m_gprs_in_use);
float_emit.ABI_PushRegisters(m_fprs_in_use, ARM64Reg::X1);

m_emit->MOVI2R(ARM64Reg::W1, m_address);
m_emit->MOV(ARM64Reg::W2, m_src_reg);
m_emit->MOVP2R(ARM64Reg::X1, &Core::System::GetInstance());
m_emit->MOVI2R(ARM64Reg::W2, m_address);
m_emit->MOV(ARM64Reg::W3, m_src_reg);
m_emit->BLR(m_emit->ABI_SetupLambda(lambda));

float_emit.ABI_PopRegisters(m_fprs_in_use, ARM64Reg::X1);
@@ -110,7 +110,7 @@ class MMIOReadCodeGenerator : public MMIO::ReadHandlingMethodVisitor<T>
{
LoadAddrMaskToReg(8 * sizeof(T), addr, mask);
}
void VisitComplex(const std::function<T(u32)>* lambda) override
void VisitComplex(const std::function<T(Core::System&, u32)>* lambda) override
{
CallLambda(8 * sizeof(T), lambda);
}
@@ -169,14 +169,14 @@ class MMIOReadCodeGenerator : public MMIO::ReadHandlingMethodVisitor<T>
}
}

void CallLambda(int sbits, const std::function<T(u32)>* lambda)
void CallLambda(int sbits, const std::function<T(Core::System&, u32)>* lambda)
{
ARM64FloatEmitter float_emit(m_emit);

m_emit->ABI_PushRegisters(m_gprs_in_use);
float_emit.ABI_PushRegisters(m_fprs_in_use, ARM64Reg::X1);

m_emit->MOVI2R(ARM64Reg::W1, m_address);
m_emit->MOVP2R(ARM64Reg::X1, &Core::System::GetInstance());
m_emit->MOVI2R(ARM64Reg::W2, m_address);
m_emit->BLR(m_emit->ABI_SetupLambda(lambda));
if (m_sign_extend)
m_emit->SBFM(m_dst_reg, ARM64Reg::W0, 0, sbits - 1);
160 Source/Core/VideoCommon/CommandProcessor.cpp
View file
@@ -239,23 +239,23 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
MMIO::InvalidWrite<u16>());
}

mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
SetCpStatusRegister();
return m_CPStatusReg.Hex;
}),
MMIO::InvalidWrite<u16>());

mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
UCPCtrlReg tmp(val);
m_CPCtrlReg.Hex = tmp.Hex;
SetCpControlRegister();
Fifo::RunGpu();
}));

mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
UCPClearReg tmp(val);
m_CPClearReg.Hex = tmp.Hex;
SetCpClearRegister();
@@ -265,79 +265,103 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());

// Some MMIOs have different handlers for single core vs. dual core mode.
mmio->Register(
base | FIFO_RW_DISTANCE_LO,
IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
{
return static_cast<u16>(fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed));
}
else
{
return static_cast<u16>(fifo.CPEnd.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.CPBase.load(std::memory_order_relaxed) + 32);
}
}) :
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
WMASK_LO_ALIGN_32BIT));
mmio->Register(base | FIFO_RW_DISTANCE_HI,
IsOnThread() ?
MMIO::ComplexRead<u16>([](u32) {
Fifo::SyncGPUForRegisterAccess();
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
{
return (fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
16;
}
else
{
return (fifo.CPEnd.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
16;
}
}) :
MMIO::ComplexRead<u16>([](u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
}),
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
const bool is_on_thread = IsOnThread();
MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_lo_r;
if (is_on_thread)
{
fifo_rw_distance_lo_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
{
return static_cast<u16>(fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed));
}
else
{
return static_cast<u16>(fifo.CPEnd.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.CPBase.load(std::memory_order_relaxed) + 32);
}
});
}
else
{
fifo_rw_distance_lo_r = MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance));
}
mmio->Register(base | FIFO_RW_DISTANCE_LO, fifo_rw_distance_lo_r,
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
WMASK_LO_ALIGN_32BIT));

MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_hi_r;
if (is_on_thread)
{
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
{
return (fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
16;
}
else
{
return (fifo.CPEnd.load(std::memory_order_relaxed) -
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
16;
}
});
}
else
{
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
});
}
mmio->Register(base | FIFO_RW_DISTANCE_HI, fifo_rw_distance_hi_r,
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
Fifo::RunGpu();
}));

mmio->Register(
base | FIFO_READ_POINTER_LO,
IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
is_on_thread ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
mmio->Register(base | FIFO_READ_POINTER_HI,
IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
}) :
MMIO::ComplexRead<u16>([](u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
}),
IsOnThread() ? MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
std::memory_order_relaxed);
}) :
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
}));

MMIO::ReadHandlingMethod<u16>* fifo_read_hi_r;
MMIO::WriteHandlingMethod<u16>* fifo_read_hi_w;
if (is_on_thread)
{
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
});
fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
std::memory_order_relaxed);
});
}
else
{
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
});
fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
});
}
mmio->Register(base | FIFO_READ_POINTER_HI, fifo_read_hi_r, fifo_read_hi_w);
}

void GatherPipeBursted()
8 Source/Core/VideoCommon/PixelEngine.cpp
View file
@@ -242,19 +242,19 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
};
for (auto& pq_reg : pq_regs)
{
mmio->Register(base | pq_reg.addr, MMIO::ComplexRead<u16>([pq_reg](u32) {
mmio->Register(base | pq_reg.addr, MMIO::ComplexRead<u16>([pq_reg](Core::System&, u32) {
return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) & 0xFFFF;
}),
MMIO::InvalidWrite<u16>());
mmio->Register(base | (pq_reg.addr + 2), MMIO::ComplexRead<u16>([pq_reg](u32) {
mmio->Register(base | (pq_reg.addr + 2), MMIO::ComplexRead<u16>([pq_reg](Core::System&, u32) {
return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) >> 16;
}),
MMIO::InvalidWrite<u16>());
}

// Control register
mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
UPECtrlReg tmpCtrl{.hex = val};

if (tmpCtrl.pe_token)
@@ -278,7 +278,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// BBOX registers, readonly and need to update a flag.
for (int i = 0; i < 4; ++i)
{
mmio->Register(base | (PE_BBOX_LEFT + 2 * i), MMIO::ComplexRead<u16>([i](u32) {
mmio->Register(base | (PE_BBOX_LEFT + 2 * i), MMIO::ComplexRead<u16>([i](Core::System&, u32) {
g_renderer->BBoxDisable();
return g_video_backend->Video_GetBoundingBox(i);
}),
4 Source/UnitTests/Core/MMIOTest.cpp
View file
@@ -121,12 +121,12 @@ TEST_F(MappingTest, ReadWriteComplex)
{
bool read_called = false, write_called = false;

m_mapping->Register(0x0C001234, MMIO::ComplexRead<u8>([&read_called](u32 addr) {
m_mapping->Register(0x0C001234, MMIO::ComplexRead<u8>([&read_called](Core::System&, u32 addr) {
EXPECT_EQ(0x0C001234u, addr);
read_called = true;
return 0x12;
}),
MMIO::ComplexWrite<u8>([&write_called](u32 addr, u8 val) {
MMIO::ComplexWrite<u8>([&write_called](Core::System&, u32 addr, u8 val) {
EXPECT_EQ(0x0C001234u, addr);
EXPECT_EQ(0x34, val);
write_called = true;