JitArm64: Fix W0 being present twice in register cache #10086
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Fixes a regression from ecf86bb. The GPR allocation_order is initialized with only 28 elements, so the 29th element ends up getting zero initialized. Very sneaky bug...
JosJuice
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Oh wow this is mean. I'm guessing this is the actual cause of the indexed paired loadstore JIT bug? |
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Nope! I found this when looking for that bug, but this does not seem to fix that bug. |
lioncash
approved these changes
Sep 5, 2021
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Fixes a regression from PR #7155.
The GPR
allocation_orderis initialized with only 28 elements, so the 29th element ends up getting zero initialized. Very sneaky bug...