Arm64Emitter: Fix encoding of size for ADD (vector) #10953
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This was causing a bug in the rounding of paired single multiplication operands. If Force25BitPrecision was called for quad registers, the element size of its ADD instruction would get treated as if it was 16 instead of the intended 64, which would cause the result of the calculation to be incorrect if the carry had to pass a 16-bit boundary. Fixes one of the two bugs reported in https://bugs.dolphin-emu.org/issues/12998.
merryhime
approved these changes
Aug 9, 2022
lioncash
approved these changes
Aug 9, 2022
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This was causing a bug in the rounding of paired single multiplication operands. If Force25BitPrecision was called for quad registers, the element size of its ADD instruction would get treated as if it was 16 instead of the intended 64, which would cause the result of the calculation to be incorrect if the carry had to pass a 16-bit boundary.
Fixes one of the two bugs reported in https://bugs.dolphin-emu.org/issues/12998.