JitArm64: Enforce correct alignment of SPR_TL

[JosJuice]

@dvessel Could you check if this solves the issue you described in #10808 (comment)?

[dvessel]

Yes it does. Thanks for the quick fix!

[Pokechu22]

Does it make sense that a 64-bit STR is being used instead of a 32-bit one? Do we know that it won't clobber anything else? (I think it's 64-bit because PPC_REG is Arm64Gen::ARM64Reg::X29, and X29 is 64-bit (W29 is 32-bit, I think?).)

[JosJuice]

It's using a 64-bit write to write to SPR_TL and SPR_TU at the same time. Jit64 does the same thing.

(The reason why the write is 64-bit is because Xresult is 64-bit, not because PPC_REG is 64-bit.)

[Pokechu22]

Ah, that seems reasonable, then.

Incidentally, I decided to check the ppc_750cl manual, which mentions (page 113/114):

The TB registers are referred to as TBRs rather than SPRs and can be written to using the mtspr instruction in supervisor mode and the TBR numbers here. The TB registers can be read in user mode using either the mftb or mfspr instruction and specifying TBR 268 for TBL and SPR 269 for TBU.

And also, page 117:

Note that the 750CL ignores the extended opcode differences between mftb and mfspr by ignoring bit 25 and treating both instructions identically.

It looks like we have mftb just call mfspr, but some of the optimisations in mfspr for TB expect it to be mftb.

It also looks like we don't handle moves to the timebase, which is probably not that important but I think I've seen it happen. The manual also mentions a mttb instruction in the table on page 239 which doesn't appear anywhere else (this PowerPC 601 manual says it exists for compatibility but just triggers an illegal instruction there (p. 263); it's probably the same case here).