JitArm64: Micro-optimizations in fres routine #11956
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Not sure why I didn't do this to begin with. Maybe I was under the impression that the most significant bit of a 12-bit immediate was a sign bit.
We want to have a low number of instructions between the LDP and the MADD so that the MADD can start immediately after the LDP finishes even if we're on a lower-end in-order CPU.
| UBFX(ARM64Reg::X1, ARM64Reg::X1, 37, 10); // Grab lower part of mantissa | ||
| LDP(IndexType::Signed, ARM64Reg::W2, ARM64Reg::W3, ARM64Reg::X2, 0); |
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I'm unfamiliar with the exact ARM in-order semantics, but can the MOVI2R(ARM64Reg::W4, 1) here be moved further up? Would that change anything?
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Yes, we could move it as far up as we want to as long as we don't move it before an instruction that uses W4/X4 (which there are none of here). But there's no scheduling benefit to doing so. This MOV can run in parallel with the LDP, assuming the CPU is capable of running instructions in parallel at all, which we kind of have to assume when deciding on scheduling since otherwise it doesn't matter how we schedule instructions.
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Gotcha, thanks for the explanation.
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I assume you tested this. Reasonable to me. |
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Even better: This code has unit tests ;) |
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