From 5d647251f71b4241aab41ca929cb0de554c0809e Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:20:18 +0200 Subject: [PATCH 1/5] JitArm64: subfic - Conditionally skip temp reg allocation --- .../Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index dd7506806420..5ebb84a5c1a6 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -1392,13 +1392,17 @@ void JitArm64::subfic(UGeckoInstruction inst) } else { - gpr.BindToRegister(d, d == a); + const bool allocate_reg = d == a; + gpr.BindToRegister(d, allocate_reg); // d = imm - a - ARM64Reg WA = gpr.GetReg(); + ARM64Reg RD = gpr.R(d); + ARM64Reg WA = allocate_reg ? gpr.GetReg() : RD; MOVI2R(WA, imm); - CARRY_IF_NEEDED(SUB, SUBS, gpr.R(d), WA, gpr.R(a)); - gpr.Unlock(WA); + CARRY_IF_NEEDED(SUB, SUBS, RD, WA, gpr.R(a)); + + if (allocate_reg) + gpr.Unlock(WA); ComputeCarry(); } From defe97d9f15d8fbe5a1968064fc2665f14178b62 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:22:38 +0200 Subject: [PATCH 2/5] JitArm64: addex - Skip temp reg allocation --- Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 5ebb84a5c1a6..fb6a4e1ac27d 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -1435,10 +1435,9 @@ void JitArm64::addex(UGeckoInstruction inst) } case CarryFlag::InHostCarry: { - ARM64Reg WA = gpr.GetReg(); - MOVI2R(WA, i + j); - ADC(gpr.R(d), WA, ARM64Reg::WZR); - gpr.Unlock(WA); + ARM64Reg RD = gpr.R(d); + MOVI2R(RD, i + j); + ADC(RD, RD, ARM64Reg::WZR); break; } case CarryFlag::ConstantTrue: From 0189692ea37f2fa3d590c72fdb1937ed56d98b83 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:26:23 +0200 Subject: [PATCH 3/5] JitArm64: divwx - Conditionally skip temp reg allocation --- .../Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index fb6a4e1ac27d..311bd31d91bc 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -1675,7 +1675,8 @@ void JitArm64::divwx(UGeckoInstruction inst) { const s32 divisor = s32(gpr.GetImm(b)); - gpr.BindToRegister(d, d == a); + const bool allocate_reg = a == d; + gpr.BindToRegister(d, allocate_reg); // Handle 0, 1, and -1 explicitly if (divisor == 0) @@ -1712,7 +1713,6 @@ void JitArm64::divwx(UGeckoInstruction inst) ARM64Reg RA = gpr.R(a); ARM64Reg RD = gpr.R(d); - const bool allocate_reg = a == d; ARM64Reg WA = allocate_reg ? gpr.GetReg() : RD; TST(RA, RA); @@ -1732,13 +1732,13 @@ void JitArm64::divwx(UGeckoInstruction inst) // Optimize signed 32-bit integer division by a constant SignedMagic m = SignedDivisionConstants(divisor); - ARM64Reg WA = gpr.GetReg(); - ARM64Reg WB = gpr.GetReg(); ARM64Reg RD = gpr.R(d); + ARM64Reg WA = gpr.GetReg(); + ARM64Reg WB = allocate_reg ? gpr.GetReg() : RD; + ARM64Reg XD = EncodeRegTo64(RD); ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XB = EncodeRegTo64(WB); - ARM64Reg XD = EncodeRegTo64(RD); SXTW(XA, gpr.R(a)); MOVI2R(XB, s64(m.multiplier)); @@ -1771,7 +1771,9 @@ void JitArm64::divwx(UGeckoInstruction inst) ADD(RD, WA, RD); } - gpr.Unlock(WA, WB); + gpr.Unlock(WA); + if (allocate_reg) + gpr.Unlock(WB); } if (inst.Rc) From f7c97ae6545c39e6b16f1634a8e649c194836904 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:36:10 +0200 Subject: [PATCH 4/5] JitArm64: srawx - Conditionally skip temp reg allocation --- Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 311bd31d91bc..dbcb6370ec37 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -2009,9 +2009,11 @@ void JitArm64::srawx(UGeckoInstruction inst) } else { - gpr.BindToRegister(a, a == b || a == s); + const bool will_read = a == b || a == s; + gpr.BindToRegister(a, will_read); - ARM64Reg WA = gpr.GetReg(); + const bool allocate_reg = will_read || js.op->wantsCA; + ARM64Reg WA = allocate_reg ? gpr.GetReg() : gpr.R(a); LSL(EncodeRegTo64(WA), EncodeRegTo64(gpr.R(s)), 32); ASRV(EncodeRegTo64(WA), EncodeRegTo64(WA), EncodeRegTo64(gpr.R(b))); @@ -2024,7 +2026,8 @@ void JitArm64::srawx(UGeckoInstruction inst) ComputeCarry(WA); } - gpr.Unlock(WA); + if (allocate_reg) + gpr.Unlock(WA); } if (inst.Rc) From b63808a652b4233dc9ebf77603f5a5a719987f01 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:38:04 +0200 Subject: [PATCH 5/5] JitArm64: rlwimix - Conditionally skip temp reg allocation --- .../Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index dbcb6370ec37..7e5817ac0c24 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -2106,15 +2106,19 @@ void JitArm64::rlwimix(UGeckoInstruction inst) else { gpr.BindToRegister(a, true); + const bool allocate_reg = a == s; + ARM64Reg RA = gpr.R(a); ARM64Reg WA = gpr.GetReg(); - ARM64Reg WB = gpr.GetReg(); + ARM64Reg WB = allocate_reg ? gpr.GetReg() : RA; MOVI2R(WA, mask); - BIC(WB, gpr.R(a), WA); + BIC(WB, RA, WA); AND(WA, WA, gpr.R(s), ArithOption(gpr.R(s), ShiftType::ROR, rot_dist)); - ORR(gpr.R(a), WB, WA); + ORR(RA, WB, WA); - gpr.Unlock(WA, WB); + gpr.Unlock(WA); + if (allocate_reg) + gpr.Unlock(WB); } if (inst.Rc)