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JitRegCache: Refactor register cache #7492
Similar idea to #3565, different implementation.
This refactor allows for easier development of future optimizations.
We introduce two new concepts,
As an example, here is what an addition of register a and register b to be stored in register d would look like:
RCX64Reg Rd = gpr.Bind(d, RCMode::Write); RCOpArg Ra = gpr.Use(a, RCMode::Read); RCOpArg Rb = gpr.Use(b, RCMode::Read); RegAlloc::Realize(Rd, Ra, Rb); MOV_sum(32, Rd, Ra, Rb);
Each declaration is a constraint, and when
There are several constraint types:
One can use
Wondering if all those members for
RCForkGuard etc. should have the
m_ prefix or not...
Nov 9, 2018
10 checks passed
Is this actually supposed to affect anything? Or just look out for regressions…
On Thu, Nov 8, 2018, 10:46 PM Pierre Bourdon ***@***.*** wrote: Merged #7492 <#7492> into master. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#7492 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AGSuQdISi9CIZZWLEqOwvibvxwWXotQeks5utPp3gaJpZM4Xas7S> .
Just look out for regressions in any games that exercise the JIT in tricky ways, I'd say.
It looks like this broke Rogue Squadron II (doesn't boot). I bisected to the