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Debugger: Get target memory in load/store instructions #7675
Debugger: Get target memory in load/store instructions #7675
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I could follow the "show in memory" context item to send the target memory address to the memory widget, rather than breakpoint or even copy it. If that's better? |
I've reviewed the first three commits. The tracing and differencing change should be in its own PR (it's 1K+ LoC on its own, not counting other things), the other changes preceding it are fine by themselves in one PR, since they're mostly related.
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Thanks for the detailed review, I'll work on it. Removing tracing and differencing. I see they should each have their own PR, though tracing does rely on this PR. |
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I found one major issue with GekkoDisassembler. On load/stores that use a register for the offset (lwzx) if the offset register value is 0, then the offset is 0 and NOT r0. All others cases are normal (offset = 1 -> r1). I don't know how to correctly fix that. I will edit my PPCDebugInterface to deal with the error instead. This error also applies to things like icbi. icbi r0, r4 should be icbi 0, r4. Also, I dealt with all listed PR issues, but left a few open for discussion. |
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Fixed offset = 0 instead of r0. |
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Fixed everything I think needs fixing. Any open issues are left open for further comment, but may not need anything done. Also tweaked: |
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Would still be nice to see this old PR get accepted. This PR has important base changes for the use of regex on PPC instructions. It is shared by my code tracing PR, which I haven't had time to work on. This would be a small, but definitely step in that direction and opening up new useful features to be added. After this PR, my plan is to implement the base tracing logic in another PR with a basic usable feature, then perhaps tackle the full code tracing PR again. |
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Side note: GekkoDisasm doesn't recognize when 0 needs to be 0 and not r0. I deal with this bug in my regex logic. lfsx f1, r0, r4 should be lfsx f1, 0, r4 for example. Too much work for me to identify every case and fix, I think. I'll check the bug reports to see if it's noted. |
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I think my commits are all good now, except for squashing. Am I expected to hit the re-request review every time I finish updating it? I don't know. |
I think my commits are all good now, except for squashing. Am I expected to hit the re-request review every time I finish updating it? I don't know.
IIRC, it sends a notification to the reviewers. I think it's fine to use it when your PR is ready to be reviewed.
…opy a load/store target memory address from instructions at or near PC when paused.
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Ok, I think we're good. |
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It's a bit silly that you're reverse-engineering the register from the disassembled instruction string, but eh, seems to work well enough. |
Backend:
Updates disassembler instructions. Mostly spaces and commas. PS load/store uses 0x notation. Required for new features.
Adds function to PPCDebugInterface to calculate target memory address for load/store instructions.
Code widget new feature:
-Context menu for copying or showing memory target in load/store instructions. Only works if the PC is near the instruction (register consistency).
/edit removed trace and diff for their own PRs
/edit2 changed breakpoint memory to 'show in memory'.