Jit64: Minor divwx optimizations #9667
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When destination and input registers match, a redundant MOV instruction can be eliminated. Before: 8B C7 mov eax,edi 8B F8 mov edi,eax C1 EF 1F shr edi,1Fh 03 F8 add edi,eax D1 FF sar edi,1 After: 8B C7 mov eax,edi C1 EF 1F shr edi,1Fh 03 F8 add edi,eax D1 FF sar edi,1
Division by a power of two can be slightly improved when the destination and dividend registers are the same. Before: 8B C6 mov eax,esi 85 C0 test eax,eax 8D 70 03 lea esi,[rax+3] 0F 49 F0 cmovns esi,eax C1 FE 02 sar esi,2 After: 85 F6 test esi,esi 8D 46 03 lea eax,[rsi+3] 0F 48 F0 cmovs esi,eax C1 FE 02 sar esi,2
We normally check for division by zero to know if we should set the destination register to zero with a XOR. However, when the divisor and destination registers are the same the explicit zeroing can be omitted. In addition, some of the surrounding branching can be simplified as well. Before: 45 85 FF test r15d,r15d 75 05 jne normal_path 45 33 FF xor r15d,r15d EB 0C jmp done normal_path: B8 5A 00 00 00 mov eax,5Ah 99 cdq 41 F7 FF idiv eax,r15d 44 8B F8 mov r15d,eax done: After: 45 85 FF test r15d,r15d 74 0C je done B8 5A 00 00 00 mov eax,5Ah 99 cdq 41 F7 FF idiv eax,r15d 44 8B F8 mov r15d,eax done:
lioncash
approved these changes
May 20, 2021
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Some of the optimizations introduced in #9566 can be tweaked to generate ever so slightly better code under specific circumstances.
Division by 2 (with d == a)
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Division by power of 2 (with d == a)
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Constant dividend (with d == b)
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