JitArm64: Improve psq_l/psq_st address checking #9884
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This makes it possible to construct flag combinations like "load 16 bits into an FPR".
EmitBackpatchRoutine (see the upcoming commits) expects the address to be in W0 for loads and W1 for stores.
In the case of the JitAsm routines, we can't actually use backpatching. Still, I would like to gather all the load and store instructions in one place to make future changes easier.
This way the address check will take up less icache (since it's only emitted once for each routine rather than once for each psq_st instruction), and we also get address checking for psq_l. Matches Jit64's approach. The disadvantage: In the slowmem case, the routines have to push *every* caller-saved register onto the stack, even though most callers probably don't need it. But at long as the slowmem case isn't hit frequently, this is fine.
Same approach as Jit64 here as well.
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psq_l and psq_st, which both do not use backpatching in the general case due to their reliance on asm routines, are rather lacking when it comes to address checking. psq_st assumes fixed BAT mappings, and psq_l has no address checking at all – if you give it a funny-looking address it will simply crash. This PR improves the situation by implementing Jit64's way of handling psq_l/psq_st address checking.