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@efabless @AUCOHL
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  1. A complete Open Source Design for Testing (DFT) Solution

    Swift 64 13

  2. Standard Cell Library based Memory Compiler using FF/Latch cells

    Verilog 52 21

  3. Oak.js Public

    Online RISC-V/MIPS Assembler & Simulator

    JavaScript 9 2

  4. OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Verilog 624 227

830 contributions in the last year

Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

June 2022

Created a pull request in The-OpenROAD-Project/OpenLane that received 7 comments

Fix Magic Antenna Check

~ Fixed issue where run_magic_antenna_check would fail to run after regression in #864 ~ Fixed issue where run_magic_antenna_check processed output…

+11 −10 7 comments
Reviewed 4 pull requests in 1 repository

Created an issue in RTimothyEdwards/open_pdks that received 7 comments

LEF/DEF with DRC errors generate GDS without any

Based on The-OpenROAD-Project/OpenLane#695. A tlef/def combo reports DRC errors when run with Magic, but running DRC on said GDS file returns 0 er…

7 comments
Opened 2 other issues in 2 repositories
The-OpenROAD-Project/OpenROAD 1 closed
efabless/volare 1 open

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