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  1. A complete Open Source Design for Testing (DFT) Solution

    Swift 65 13

  2. Standard Cell Library based Memory Compiler using FF/Latch cells

    Verilog 53 21

  3. Oak.js Public

    Online RISC-V/MIPS Assembler & Simulator

    JavaScript 9 2

  4. OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Verilog 628 229

815 contributions in the last year

Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

July 2022

Created 1 commit in 1 repository
Reviewed 1 pull request in 1 repository
The-OpenROAD-Project/OpenLane 1 pull request

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