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  1. A complete open-source design-for-testing (DFT) Solution

    Swift 74 14

  2. Standard Cell Library based Memory Compiler using FF/Latch cells

    Verilog 60 26

  3. Oak.js Public

    Online RISC-V/MIPS Assembler & Simulator

    JavaScript 9 2

  4. OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Verilog 723 253

763 contributions in the last year

Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Mon Wed Fri

Contribution activity

September 2022

Created 2 repositories

Created a pull request in cemu-project/Cemu that received 3 comments

AppImage Investigation

I tried my hand at this to see how far I'd get. I compiled Cemu on a Docker image running CentOS 7 as it's reasonably old (the older your Glibc is,…

+434 −0 3 comments
Opened 9 other pull requests in 2 repositories

Created an issue in The-OpenROAD-Project/OpenROAD that received 11 comments

Crash during global placement

Using OpenROAD 4174c3a OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e This program is licensed under the BSD-3 license. See the LICENSE file f…


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